Minutes of the third WorldFIP insourcing meeting
11 June 2009, room 865-1d17
Present: Fabio Formenti, Julien Palluel, Erik van der Bij, Quentin King (some minutes before the meeting), Giovanni Spiezia, Gonzalo Fernández Peñacoba, Benjamin Todd, Javier Serrano.
- Javier introduced Giovanni as a new project team member. Giovanni will be mainly concerned with Work Package 9 (Radiation tests).
- Quentin was in a hurry because of a clash with another meeting. He
gave his comments on the Functional Specs document sent around by
Erik:
- Setting up a bus arbiter is a costly and complicated process. It's usually done once and for all at the beginning of time. This means that the proposal of having a different variable to trigger resets remotely might be impractical. Using contents of a predefined variable could be considered instead. E.g if the first byte of the consumed variable contains the address of the station, it could reset this station. One possible implementation is to have an output pin showing that this condition is met, and feeding it back externally as a reset. This would leave the option to have standard data.
- Storing the length of received variables would be good. This could be as the first byte or word of the data stored in the memory, before the data. Some comments during Erik's presentation point in the same direction.
- Erik gave a presentation on the
preliminary functional spec.
- There was some discussion about the suitability of Wishbone as
an external bus to be interfaced to user logic. No
microcontroller can interface directly to it. In the end it was
decided not to change because:
- People in radiation areas would not be using microcontrollers.
- People in non-sensitive areas are free to take our HDL and extend it with a Wishbone to uController adapter to suit their particular needs.
- Fabio saw the lack of a proper handshake as a weak point of the interface between this chip and the user logic. Javier answered that in this application, "late data is wrong data". At the end we all agreed that at least we should explore ways of pushing status information up to the BA if anything goes wrong, but respecting both WorldFIP compliance and simplicity as a basis of robustness.
- There was a question on the preliminary choice for FPGA technology. Erik and Javier answered that flash-based Actel seems to be the favored solution in the experiments after quite a lot of tests. There is in principle no reason to depart from that choice, but this will be analyzed in due time. Comment from Gonzalo after the meeting: we should conduct radiation tests of both flash and antifuse-based devices, and compare the results.
- There was some discussion about the suitability of Wishbone as
an external bus to be interfaced to user logic. No
microcontroller can interface directly to it. In the end it was
decided not to change because:
- Javier said some words on the agenda for the Summer:
- Functional spec and technical spec work will overlap:
- On the func spec side, Erik will polish his document with feedback from Quentin, Gonzalo and others and then submit it to all the clients for EDMS approval.
- On the technical side, Erik and Javier will draw a preliminary block diagram of the inside of the chip and use the "informal spec" technique to specify these different blocks.
- A summer student will work for two months starting in July on global test benches for the chip. At the same time BE-CO-HT will start the design of the chip proper.
- The next meeting will be after the summer holidays, hopefully with some technical results to present.
- Since PCB design is a long process, we should start thinking of good candidates for putting together an Actel FPGA and a FielDrive plus the associated magnetics into a PCB that could then become a useful piece of hardware for one of the clients. The FGC Lite seems to be a good option. Erik and Javier will discuss the details with Quentin.
- Functional spec and technical spec work will overlap:
- Since we are starting to generate quite a lot of documentation, it would be good to settle on new names. CERNFip is perceived by Raymond as not very export-friendly because it contains "CERN". It was decided to rename the project to "ScientiFIP" and the MicroFIP replacement chip as "NanoFIP".
J.Serrano, E.Van der Bij, June 2009