bit-banged JTAG lines to 'Z' when not used
In the current configuration, nanoFIP keeps bitbanged JTAG lines at '1' (TCK) or '0' (TMS, TDI) when JTAG is not used. This makes it impossible to have a carrier with the main FPGA and a JTAG connector used e.g. to reprogram this main FPGA using FlashPro cable during development. The only possibility would be to have some muxes to select which JTAG source should be used.
Could we instead keep bitbanged JTAG lines at 'Z' when JTAG of nanoFIP is not used? @egousiou were there any other constraints when nanoFIP was developed that prevented this?