Commit dd9fa4bf authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎

modify reset values

parent f85943a5
......@@ -185,7 +185,7 @@ architecture rtl of wf_reset_unit is
signal rstin_st, nx_rstin_st : rstin_st_t;
-- RSTIN counter
signal s_rstin_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH+1 downto 0);
signal s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH+3 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_three : std_logic;
signal s_rstin_c_is_seven, s_rstin_c_is_4txck : std_logic;
signal s_rstin_c_is_full : std_logic;
......@@ -206,7 +206,7 @@ architecture rtl of wf_reset_unit is
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
-- need to extend pulse to reset carrier
signal s_txck_32_periods : unsigned (c_2_PERIODS_COUNTER_LGTH+1 downto 0);
signal s_txck_32_periods : unsigned (c_2_PERIODS_COUNTER_LGTH+3 downto 0);
--=================================================================================================
-- architecture begin
......@@ -663,7 +663,7 @@ RSTIN_free_counter: wf_incr_counter
-- s_var_rst_c_is_full will be activated and the FSM will be reset.
free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH+2)
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH+4)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var_rst_c_reinit,
......@@ -674,9 +674,9 @@ free_counter: wf_incr_counter
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_c_is_seven <= '1' when s_var_rst_c = to_unsigned(7, s_var_rst_c'length) else '0';
s_var_rst_c_is_three <= '1' when s_var_rst_c = to_unsigned(3, s_var_rst_c'length) else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_32_periods -1 else '0';
s_var_rst_c_is_seven <= '1' when s_var_rst_c = to_unsigned(32768, s_var_rst_c'length) else '0';
s_var_rst_c_is_three <= '1' when s_var_rst_c = to_unsigned(16384, s_var_rst_c'length) else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_32_periods -1 else '0';
......
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