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nanoFIP - Gateware
Commit b1b865e3 authored by egousiou's avatar egousiou
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modif after code review 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@251 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 5de66e26
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nanofip.vhd
View file @ b1b865e3
......@@ -19,9 +19,9 @@
-- ProASIC3 Flash family FPGA (130nm CMOS technology) that offers an inherent resistance to |
-- radiation: it is immune to Single Event Latchups for the LHC environment, it has high tolerance|
-- to Total Ionizing Dose effects (>300 Gy) and its configuration memory is not disturbed by SEUs.|
-- Another feature that nanoFIP offers is the possibility to reprogram the user logic through |
-- Another feature that nanoFIP offers is the possibility to reprogram the user logic FPGA through|
-- JTAG interface; WorldFIP frames are translated to the equivalent JTAG signals that drive and |
-- control the user logic Test Access Port (TAP) controller. |
-- monitor the user logic Test Access Port controller (TAP). |
-- nanoFIP is used in conjunction with a FIELDRIVE chip and FIELDTR insulating transformer, |
-- both available from the company ALSTOM. |
-- |
......@@ -112,7 +112,7 @@
-- |
-- o wf_fd_transmitter : for the serialization of produced RP_DAT frames |
-- |
-- o wf_production : for the retreival of bytes for produced RP_DAT frames |
-- o wf_production : for the retrieval of bytes for produced RP_DAT frames |
-- |
-- o wf_engine_control : for the processing of the ID_DAT frames and the coordination of the |
-- wf_consumption, wf_fd_receiver, wf_production & wf_fd_transmitter units|
......@@ -123,8 +123,8 @@
-- o wf_wb_controller : for the handling of the "User Interface WISHBONE Slave" control |
-- signals |
-- |
-- o wf_jtag_controller : for driving and controlling the user logic TAP controller upon |
-- reception of JTAG variables (aa_xy and ab_xy). |
-- o wf_jtag_controller : for driving and monitoring the user logic TAP upon reception of JTAG |
-- variables (aa_xy and ab_xy). |
-- |
-- _____________ ____________________________________________________ |
-- | | | wf_WB_controller | |
......
wf_cons_bytes_processor.vhd
View file @ b1b865e3
......@@ -173,7 +173,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Memory mode Consumed & Consumed Broadcast RAM --
-- Storage (by the unit) & retreival (by the user) of consumed bytes --
-- Storage (by the unit) & retrieval (by the user) of consumed bytes --
---------------------------------------------------------------------------------------------------
-- Instantiation of a 512 x 8 Dual Port RAM, for both the consumed and consumed broadcast vars
-- Port A is connected to the WISHBONE interface for the readings from the user
......@@ -195,12 +195,12 @@ begin
---------------------------------------------------------------------------------------------------
-- JTAG Consumed RAM --
-- Storage (by this unit) & retreival (by the JTAG_controller unit) of consumed bytes --
-- Storage (by this unit) & retrieval (by the JTAG_controller unit) of consumed bytes --
---------------------------------------------------------------------------------------------------
-- Instantiation of a 512 x 8 Dual Port RAM for the storage of var_4 variables.
-- Only 127 bytes of memory are used.
-- nanoFIP's user clock uclk is connected to both ports of the memory; the writing of the
-- consumed data and the reading of them (by the wf_jtag_controller) take place internally.
-- Note: only 127 bytes are used.
Consumption_JTAG_RAM : wf_dualram_512x8_clka_rd_clkb_wr
port map(
......
wf_engine_control.vhd
View file @ b1b865e3
......@@ -52,8 +52,8 @@
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG E0 added as broadcast |
-- PDU,LGTH,CTRL bytes of RP_DAT checked bf VAR1_RDY/var_2_rdy assertion; |
-- if ID_DAT>8 bytes or RP_DAT>133 (bf reception of a FES) go to idle; |
-- state consume_wait_FSS, for the correct use of the silence time(time |
-- if ID_DAT>8 bytes or RP_DAT>133 (bf reception of a FES) go to IDLE; |
-- state CONSUME_WAIT_FSS, for the correct use of the silence time(time |
-- stops counting when an RP_DAT frame has started) |
-- 12/2010 v0.03 EG state machine rewritten moore style; removed check on slone mode |
-- for #bytes>4; in slone no broadcast |
......@@ -61,12 +61,12 @@
-- assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and |
-- rx_byte_ready_p_o removed cleaning-up+commenting |
-- 02/2011 v0.05 EG Independent timeout counter added; time counter 18 digits instead of 15|
-- id_dat_frame_ok: corrected mistake if rx_fss_crc_fes_ok_p not |
-- ID_DAT_FRAME_OK: corrected mistake if rx_fss_crc_fes_ok_p not |
-- activated; rx reset during production (rx_rst_o); |
-- cons_bytes_excess_o added |
-- tx_completed_p_i added (bf for the engine ctrl production was finished |
-- after the delivery of the last data byte (MPS)) |
-- 07/2011 v0.06 EG rst_rx state added |
-- 07/2011 v0.06 EG RST_RX state added |
-- 10/2011 v0.06b EG moved session_timedout in the synchronous FSM process |
---------------------------------------------------------------------------------------------------
......@@ -192,10 +192,10 @@ end entity wf_engine_control;
architecture rtl of wf_engine_control is
-- FSM
type control_st_t is (idle,
id_dat_control_byte, id_dat_var_byte, id_dat_subs_byte, id_dat_frame_ok,
consume_wait_FSS, consume, rst_rx,
produce_wait_turnar_time, produce);
type control_st_t is (IDLE,
ID_DAT_CTRL_BYTE, ID_DAT_VAR_BYTE, ID_DAT_SUBS_BYTE, ID_DAT_FRAME_OK,
CONSUME_WAIT_FSS, CONSUME, RST_RX,
PRODUCE_WAIT_TURNAR_TIME, PRODUCE);
signal control_st, nx_control_st : control_st_t;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_frame_ok : std_logic;
signal s_cons_wait_FSS, s_consuming, s_rst_rx_p : std_logic;
......@@ -234,31 +234,32 @@ begin
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- The FSM stays in idle until the reception of a FSS from the wf_fd_receiver.
-- The FSM stays in IDLE until the reception of a FSS from the wf_fd_receiver.
-- It continues by checking one by one the bytes of the frame as they arrive:
-- o if the CTRL byte corresponds to an ID_DAT,
-- o if the variable byte corresponds to a defined variable,
-- o if the subscriber byte matches the station's address, or if the variable is a broadcast
-- o and if the frame finishes with a correct CRC and FES.
-- If any of the bytes above has been different than the expected, the FSM resets the wf_fd_receiver
-- and goes back to IDLE.
-- o if the ID_DAT frame has been correct and the received variable is a produced (var_presence,
-- o if the ID_DAT frame has been correct and the received variable is a produced (var_presence,
-- var_identif, var_3, var_5) the FSM stays in the "produce_wait_turnar_time" state until the
-- expiration of the turnaround time and then jumps to the "produce" state, waiting for the
-- var_identif, var_3, var_5) the FSM stays in the "PRODUCE_WAIT_TURNAR_TIME" state until the
-- expiration of the turnaround time and then jumps to the "PRODUCE" state, waiting for the
-- wf_fd_serializer to finish the transmission; then it goes back to IDLE.
-- o if the received variable is a consumed (var_1, var_2, var_rst, var_4) the FSM stays in the
-- o if the received variable is a consumed (var_1, var_2, var_rst, var_4) the FSM stays in the
-- "consume_wait_FSS" state until the arrival of a FSS or the expiration of the silence time.
-- "CONSUME_WAIT_FSS" state until the arrival of a FSS or the expiration of the silence time.
-- After the arrival of the FSS the FSM jumps to the "CONSUME" state, where it stays until the
-- end of the reception of the consumed frame (marked by a FES).
-- Note: In the case of a var_5, it is the wf_consumption unit that signals the start-up of
-- Note: In the case of a var_5, it is the wf_consumption unit that signals the start-up of
-- the wf_jtag_controller which will work in parallel and independently from the
-- wf_engine_control; i.e. new frames reception can take place while the
-- wf_jtag_controller is working.
-- wf_jtag_controller is working.
-- To add a rubust layer of protection to the FSM, a counter dependant only on the system clock
-- To add a robust layer of protection to the FSM, a counter dependent only on the system clock
-- has been implemented, that from any state can bring the FSM back to IDLE. At any bit rate the
-- reception of an ID_DAT frame followed by the reception/ transmission of an RP_DAT should not
-- reception of an ID_DAT frame followed by the reception/ transmission of an RP_DAT should not
-- last more than 37ms. Hence, we have generated a 21 bits counter that will reset the machine
-- last more than 41ms. Hence, we have generated a 21 bits (c_SESSION_TIMEOUT_C_LGTH)counter that
-- will reset the machine if more than 52ms (complete 21 bit counter) have passed since it has
-- left this IDLE state.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Engine_Control_FSM_Sync: storage of the current state of the FSM
......@@ -267,7 +268,7 @@ begin
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_session_timedout = '1' then
control_st <= idle;
control_st <= IDLE;
else
control_st <= nx_control_st;
end if;
......@@ -290,49 +291,49 @@ begin
case control_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when idle =>
when IDLE =>
if rx_fss_received_p_i = '1' then -- new frame FSS detected
nx_control_st <= id_dat_control_byte;
nx_control_st <= ID_DAT_CTRL_BYTE;
else
nx_control_st <= idle;
nx_control_st <= IDLE;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_control_byte =>
when ID_DAT_CTRL_BYTE =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i(5 downto 0) = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte; -- check of ID_DAT CTRL byte
nx_control_st <= ID_DAT_VAR_BYTE; -- check of ID_DAT CTRL byte
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= rst_rx; -- byte different than the expected ID_DAT CTRL
nx_control_st <= RST_RX; -- byte different than the expected ID_DAT CTRL
else
nx_control_st <= id_dat_control_byte;-- ID_DAT CTRL byte being arriving
nx_control_st <= ID_DAT_CTRL_BYTE; -- ID_DAT CTRL byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_var_byte =>
when ID_DAT_VAR_BYTE =>
if (rx_byte_ready_p_i = '1') and (s_var_identified = '1') then
nx_control_st <= id_dat_subs_byte; -- check of the ID_DAT variable
nx_control_st <= ID_DAT_SUBS_BYTE; -- check of the ID_DAT variable
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= rst_rx; -- byte not corresponding to an expected variable
nx_control_st <= RST_RX; -- byte not corresponding to an expected variable
else
nx_control_st <= id_dat_var_byte; -- ID_DAT variable byte being arriving
nx_control_st <= ID_DAT_VAR_BYTE; -- ID_DAT variable byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_subs_byte =>
when ID_DAT_SUBS_BYTE =>
if (rx_byte_ready_p_i = '1') and ((rx_byte_i = subs_i) or (s_broadcast_var = '1')) then
nx_control_st <= id_dat_frame_ok; -- checking of the ID_DAT subscriber
nx_control_st <= ID_DAT_FRAME_OK; -- checking of the ID_DAT subscriber
-- or if it is a broadcast variable
-- note: broadcast consumed vars are only treated in
-- memory mode, but at this moment we do not do this
......@@ -340,90 +341,91 @@ begin
-- also in stand-alone mode.
elsif rx_byte_ready_p_i = '1' then -- not the station's address, neither a broadcast var
nx_control_st <= rst_rx;
nx_control_st <= RST_RX;
else
nx_control_st <= id_dat_subs_byte; -- ID_DAT subscriber byte being arriving
nx_control_st <= ID_DAT_SUBS_BYTE; -- ID_DAT subscriber byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_frame_ok =>
when ID_DAT_FRAME_OK =>
if (rx_fss_crc_fes_ok_p_i = '1') and (s_prod_or_cons = "10") then
nx_control_st <= produce_wait_turnar_time; -- ID_DAT frame ok! station has to produce
nx_control_st <= PRODUCE_WAIT_TURNAR_TIME; -- ID_DAT frame ok! station has to PRODUCE
elsif (rx_fss_crc_fes_ok_p_i = '1') and (s_prod_or_cons = "01") then
nx_control_st <= consume_wait_FSS; -- ID_DAT frame ok! station has to consume
nx_control_st <= CONSUME_WAIT_FSS; -- ID_DAT frame ok! station has to CONSUME
elsif (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber
nx_control_st <= rst_rx; -- byte, a FES has not been detected
nx_control_st <= RST_RX; -- byte, a FES has not been detected
else
nx_control_st <= id_dat_frame_ok; -- CRC & FES bytes being arriving
nx_control_st <= ID_DAT_FRAME_OK; -- CRC & FES bytes being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce_wait_turnar_time =>
when PRODUCE_WAIT_TURNAR_TIME =>
if s_time_c_is_zero = '1' then -- turnaround time passed
nx_control_st <= produce;
nx_control_st <= PRODUCE;
else
nx_control_st <= produce_wait_turnar_time; -- waiting for turnaround time to pass
nx_control_st <= PRODUCE_WAIT_TURNAR_TIME; -- waiting for turnaround time to pass
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume_wait_FSS =>
when CONSUME_WAIT_FSS =>
if rx_fss_received_p_i = '1' then -- FSS of the consumed RP_DAT arrived
nx_control_st <= consume;
nx_control_st <= CONSUME;
elsif s_time_c_is_zero = '1' then -- if the FSS of the consumed RP_DAT frame doesn't
nx_control_st <= rst_rx; -- arrive before the expiration of the silence time,
-- the engine goes back to idle
nx_control_st <= RST_RX; -- arrive before the expiration of the silence time,
-- the engine goes back to IDLE
else
nx_control_st <= consume_wait_FSS; -- counting silence time
nx_control_st <= CONSUME_WAIT_FSS; -- counting silence time
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume =>
when CONSUME =>
if (rx_fss_crc_fes_ok_p_i = '1') or -- the cons frame arrived to the end, as expected
(rx_crc_wrong_p_i = '1') then -- FES detected but wrong CRC or wrong # bits
nx_control_st <= idle;
nx_control_st <= RST_RX; -- resetting the rx is not essential in this case,
-- but for robustness reasons we decided to add it
elsif (s_rx_bytes_c > c_MAX_FRAME_BYTES) then -- no FES detected after the max number of bytes
nx_control_st <= rst_rx;
nx_control_st <= RST_RX;
else
nx_control_st <= consume; -- consuming bytes
nx_control_st <= CONSUME; -- consuming bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce =>
when PRODUCE =>
if tx_completed_p_i = '1' then -- end of production (including CRC and FES)
nx_control_st <= idle;
nx_control_st <= IDLE;
else
nx_control_st <= produce; -- producing bytes
nx_control_st <= PRODUCE; -- producing bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when rst_rx => -- the current reception has finished
when RST_RX => -- the current reception has finished
-- a reset pulse is sent to the wf_receiver
nx_control_st <= idle; -- which will start looking for a new FSS
nx_control_st <= IDLE; -- which will start looking for a new FSS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
nx_control_st <= idle;
when others =>
nx_control_st <= IDLE;
end case;
end process;
......@@ -436,7 +438,7 @@ begin
case control_st is
when idle =>
when IDLE =>
---------------------------------
s_idle_state <= '1';
......@@ -451,9 +453,9 @@ begin
s_producing <= '0';
when id_dat_control_byte =>
when ID_DAT_CTRL_BYTE =>
s_idle_state <= '0';
s_idle_state <= '0';
---------------------------------
s_id_dat_ctrl_byte <= '1';
---------------------------------
......@@ -466,7 +468,7 @@ begin
s_producing <= '0';
when id_dat_var_byte =>
when ID_DAT_VAR_BYTE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -481,7 +483,7 @@ begin
s_producing <= '0';
when id_dat_subs_byte =>
when ID_DAT_SUBS_BYTE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -494,7 +496,7 @@ begin
s_producing <= '0';
when id_dat_frame_ok =>
when ID_DAT_FRAME_OK =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -509,7 +511,7 @@ begin
s_producing <= '0';
when produce_wait_turnar_time =>
when PRODUCE_WAIT_TURNAR_TIME =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -524,7 +526,7 @@ begin
s_producing <= '0';
when consume_wait_FSS =>
when CONSUME_WAIT_FSS =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -539,7 +541,7 @@ begin
s_producing <= '0';
when consume =>
when CONSUME =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -554,7 +556,7 @@ begin
s_producing <= '0';
when rst_rx =>
when RST_RX =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -569,7 +571,7 @@ begin
s_producing <= '0';
when produce =>
when PRODUCE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -627,8 +629,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter for the counting of the number of the bytes that are
-- being produced. The counter is reset at the "produce_wait_turnar_time" state of the FSM and
-- counts bytes following the "tx_byte_request_p_i" pulse in the "produce" state.
-- being produced. The counter is reset at the "PRODUCE_WAIT_TURNAR_TIME" state of the FSM and
-- counts bytes following the "tx_byte_request_p_i" pulse in the "PRODUCE" state.
Prod_Bytes_Counter: wf_incr_counter
generic map(g_counter_lgth => 8)
......@@ -655,10 +657,10 @@ begin
-- frame (hence the name of the counter is s_rx_bytes_c and not s_cons_bytes_c).
-- Regarding an ID_DAT frame: the FSS, CTRL, var and SUBS bytes are being followed by the
-- Engine_Control_FSM; the counter is used for the counting of the bytes from then on and until
-- the arrival of a FES. Therefore, the counter is reset at the "id_dat_subs_byte" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "id_dat_frame_ok" state.
-- Regarding a RP_DAT frame : the counter is reset at the "consume_wait_FSS" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "consume" state.
-- the arrival of a FES. Therefore, the counter is reset at the "ID_DAT_SUBS_BYTE" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "ID_DAT_FRAME_OK" state.
-- Regarding a RP_DAT frame : the counter is reset at the "CONSUME_WAIT_FSS" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "CONSUME" state.
Rx_Bytes_Counter: wf_incr_counter
generic map(g_counter_lgth => 8)
......@@ -682,10 +684,10 @@ begin
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_decr_counter relying only on the system clock as an additional
-- way to go back to Idle state, in case any other logic is being stuck.
-- way to go back to IDLE state, in case any other logic is being stuck.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => 21)
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
......@@ -718,7 +720,7 @@ begin
-- to either the turnaround or the silence time. If after the correct arrival of an ID_DAT frame
-- the identified variable is a produced one the counter loads to the turnaround time, whereas if
-- it had been a consumed variable it loads to the silence. The counting takes place during the
-- states "produce_wait_turnar_time" and "consume_wait_FSS" respectively.
-- states "PRODUCE_WAIT_TURNAR_TIME" and "CONSUME_WAIT_FSS" respectively.
Turnaround_and_Silence_Time_Counter: wf_decr_counter
generic map(g_counter_lgth => 18)
......@@ -750,8 +752,8 @@ begin
-- o output signal var_o (or s_var, used also internally by the wf_prod_data_lgth_calc) that
-- locks to the value of the ID_DAT.Identifier.Variable byte at the end of the reception of a
-- valid ID_DAT frame, if the received SUBS byte matches the station's address.
-- For a produced var this takes place at the "produce_wait_turnar_time" state, and
-- for a consumed at the "consume" state (not in the "consume_wait_silence_time", as at this
-- For a produced var this takes place at the "PRODUCE_WAIT_TURNAR_TIME" state, and
-- for a consumed at the "CONSUME" state (not in the "consume_wait_silence_time", as at this
-- state there is no knowledge that a consumed RP_DAT frame will indeed arrive!).
-- (the process is very simple but very big as we decided not to use a for loop:s)
......@@ -906,7 +908,7 @@ begin
cons_byte_index_o <= std_logic_vector (s_rx_bytes_c);
-- The wf_fd_receiver receives a 1 uclk long reset pulse if during the reception of an ID or an
-- RP_DAT the engine control FSM has to go back to idle.
-- RP_DAT the engine control FSM has to go back to IDLE.
-- This may happen if : any of the CTRL, variable, subs bytes of an ID_DAT frame are wrong or
-- an ID_DAT is lasting more than 8 bytes or
-- an RP_DAT is lasting more than 133 bytes or
......
wf_jtag_controller.vhd
View file @ b1b865e3
......@@ -43,6 +43,7 @@
-- 09/2011 v0.02 EG added counter for counting the outgoing TMS/TDI bits; combinatorial |
-- was too heavy; changed a bit state machine to include counter |
-- put session_timedout in the synchronous FSM process |
-- 11/2011 v0.021 EG timeout counter has different size (constant added) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -112,9 +113,9 @@ end entity wf_jtag_controller;
--=================================================================================================
architecture rtl of wf_jtag_controller is
-- FSM
type jc_st_t is (idle, get_byte, play_byte, set_address);
type jc_st_t is (IDLE, GET_BYTE, PLAY_BYTE, SET_ADDR);
signal jc_st, nx_jc_st : jc_st_t;
signal s_idle, s_play_byte, s_set_adr : std_logic;
signal s_idle, s_play_byte, s_set_addr : std_logic;
signal s_not_play_byte : std_logic;
signal s_session_timedout : std_logic;
-- bytes counter
......@@ -150,15 +151,14 @@ begin
-- the JC_consumed memory. The first two bytes concatenated in big endian encoding indicate the
-- total amount of TMS/ TDI bits that have to be retrieved and output.
-- The rest of the bytes contain the TMS/ TDI bits.
-- The FSM goes back to idle if the counter that counts the amount the bits that have been output
-- The FSM goes back to IDLE if the counter that counts the amount the bits that have been output
-- reaches the total amount.
-- To add a robust layer of protection to the FSM, we have implemented a counter, dependant only on
-- the system clock, that from any state can bring the FSM back to idle. A frame with the maximum
-- number of TMS/ TDI bits needs a bit more than (488 bits * JC_TCK period) seconds to be treated.
-- For a 5 MHz JC_TCK clock this is around 100 us. In order to be coherent with the timeouts of the
-- other FSMs of nanoFIP, we use a 21 bits counter; therefore, the FSM is reset if 52 ms have passed
-- since it has left the idle state.
-- To add a robust layer of protection to the FSM, we have implemented a counter, dependent only on
-- the system clock, that from any state can bring the FSM back to IDLE. A frame with the maximum
-- number of TMS/ TDI bits needs: 122 bytes * ((4 * JC_TCK) + 2 uclk) seconds to be treated.
-- For a 5 MHz JC_TCK clock this is 103.7 us. We use a counter of 13 bits which means that the FSM
-- is reset if 204.8 us have passed since it has left the IDLE state.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process JC_FSM_Sync: storage of the current state of the FSM
......@@ -167,7 +167,7 @@ begin
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_session_timedout = '1' then
jc_st <= idle;
jc_st <= IDLE;
else
jc_st <= nx_jc_st;
end if;
......@@ -186,51 +186,51 @@ begin
case jc_st is
when idle =>
when IDLE =>
if jc_start_p_i = '1' then -- consumed var_4 frame validated
nx_jc_st <= set_address;
nx_jc_st <= SET_ADDR;
else
nx_jc_st <= idle;
nx_jc_st <= IDLE;
end if;
when set_address =>
nx_jc_st <= get_byte; -- 1 uclk cycle for the setting of the memory
when SET_ADDR =>
nx_jc_st <= GET_BYTE; -- 1 uclk cycle for the setting of the memory
-- address; byte available at the next cycle
when get_byte =>
when GET_BYTE =>
if s_bytes_c < 2 then -- 2 first bytes: amount of JC_TMS & JC_TDI bits
nx_jc_st <= set_address;
nx_jc_st <= SET_ADDR;
else -- the rest of the bytes have to be "played"
nx_jc_st <= play_byte;
nx_jc_st <= PLAY_BYTE;
end if;
when play_byte =>
when PLAY_BYTE =>
if s_frame_bits <= 0 or s_frame_bits > c_MAX_FRAME_BITS then
nx_jc_st <= idle; -- outside expected limits
nx_jc_st <= IDLE; -- outside expected limits
elsif s_frame_bits > s_bits_so_far then -- still available bits to go..
if s_tck_c_is_full = '1' then-- byte completed; a new one has
nx_jc_st <= set_address; -- to be retrieved
nx_jc_st <= SET_ADDR; -- to be retrieved
else -- byte being output
nx_jc_st <= play_byte;
nx_jc_st <= PLAY_BYTE;
end if;
else -- last bit
if s_tck_r_edge_p = '1' or s_tck_f_edge_p = '1' then
nx_jc_st <= idle; -- wait until the completion of a JC_TCK cycle
nx_jc_st <= IDLE; -- wait until the completion of a JC_TCK cycle
else
nx_jc_st <= play_byte;
nx_jc_st <= PLAY_BYTE;
end if;
end if;
when others =>
nx_jc_st <= idle;
when OTHERS =>
nx_jc_st <= IDLE;
end case;
end process;
......@@ -242,44 +242,44 @@ begin
case jc_st is
when idle =>
when IDLE =>
-----------------------------
s_idle <= '1';
-----------------------------
s_set_adr <= '0';
s_set_addr <= '0';
s_play_byte <= '0';
when set_address =>
when SET_ADDR =>
s_idle <= '0';
-----------------------------
s_set_adr <= '1';
s_set_addr <= '1';
-----------------------------
s_play_byte <= '0';
when get_byte =>
when GET_BYTE =>
s_idle <= '0';
s_set_adr <= '0';
s_set_addr <= '0';
s_play_byte <= '0';
when play_byte =>
when PLAY_BYTE =>
s_idle <= '0';
s_set_adr <= '0';
s_set_addr <= '0';
-----------------------------
s_play_byte <= '1';
-----------------------------
when others =>
when OTHERS =>
-----------------------------
s_idle <= '1';
-----------------------------
s_set_adr <= '0';
s_set_addr <= '0';
s_play_byte <= '0';
end case;
......@@ -360,7 +360,7 @@ begin
port map(
uclk_i => uclk_i,
counter_reinit_i => s_idle,
counter_incr_i => s_set_adr,
counter_incr_i => s_set_addr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_bytes_c);
......@@ -396,13 +396,13 @@ begin
---------------------------------------------------------------------------------------------------
-- Frame bits retreival --
-- Frame bits retrieval --
---------------------------------------------------------------------------------------------------
-- Construction of the 16 bits word that indicates the amount of TMS/ TDI bits that have to be
-- played from this frame. The word is the result of the big endian concatenation of the 1st and
-- 2nd data bytes from the memory.
Bits_Number_Retreival: process (uclk_i)
Bits_Number_retrieval: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -412,10 +412,10 @@ begin
else
s_bytes_c_d1 <= s_bytes_c;
if s_set_adr = '1' and s_bytes_c_d1 = 0 then
if s_set_addr = '1' and s_bytes_c_d1 = 0 then
s_frame_bits_msb <= jc_mem_data_i;
end if;
if s_set_adr = '1' and s_bytes_c_d1 = 1 then
if s_set_addr = '1' and s_bytes_c_d1 = 1 then
s_frame_bits_lsb <= jc_mem_data_i;
end if;
end if;
......@@ -431,7 +431,7 @@ begin
-- TMS and TDI player --
---------------------------------------------------------------------------------------------------
-- Delivery of the jc_tms_o and jc_tdi_o bits on the falling edge of the jc_tck_o clock.
-- At the "play_byte" state of the FSM the incoming jc_mem_data_i byte is decomposed to 4 TMS and
-- At the "PLAY_BYTE" state of the FSM the incoming jc_mem_data_i byte is decomposed to 4 TMS and
-- 4 TDI bits; a pair of TMS/ TDI bits is output on every TCK falling edge.
JC_TMS_TDI_player: process (uclk_i)
......@@ -472,6 +472,11 @@ begin
-- Sampling of the jc_tdo_i input on the rising edge of the jc_tck_o clock. Only the last sampled
-- bit is significant and is delivered.
-- Note: on the side of the target TAP, the jc_tdo should be provided on the falling edge of jc_tck;
-- a falling jc_tck edge comes many uclk cycles before a rising one, which is nanoFIP's sampling
-- moment for jc_tdo; therefore on the rising edges, jc_tdo is not expected to be metastable.
-- That is why we have decided not to synchronize the jc_tdo input.
JC_TDO_sampling: process (uclk_i)
begin
......@@ -493,10 +498,10 @@ begin
-- Independent Timeout Counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_decr_counter relying only on the system clock, as an additional
-- way to go back to Idle state, in case any other logic is being stuck. The timeout is 52 ms.
-- way to go back to Idle state, in case any other logic is being stuck. The timeout is 204.8 us.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => 21)
generic map(g_counter_lgth => c_JC_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
......
wf_package.vhd
View file @ b1b865e3
......@@ -27,6 +27,7 @@
-- 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics |
-- added CTRL bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG |
-- 2/2011 v0.05 EG JTAG variables added |
-- 11/2011 v0.06 EG c_SESSION_TIMEOUT_C_LGTH, c_JTAG_TIMEOUT_C_LGTH added |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -68,6 +69,68 @@ package wf_package is
constant c_QUARTZ_PERIOD : real := 25.0;
---------------------------------------------------------------------------------------------------
-- Constants regarding the JTAG controller --
---------------------------------------------------------------------------------------------------
constant c_MAX_FRAME_BITS : natural := 976; -- maximum number of TMS/ TDI bits that can be sent
-- in one frame : 122 bytes * 8 bits
constant c_FOUR_JC_TCK_C_LGTH : natural := 5; -- length of a counter counting 4 JC_TCK periods;
-- the JC_TCK frequency is defined by this constant.
-- ex: 5 MHz JC_TCK period = 200 ns = 4 uclk periods,
-- 4 JC_TCK periods = 16 uclk, hence 5 bits counter.
-- Use c_FOUR_JC_TCK_C_LGTH = 6 for a 2.5 MHz JC_TCK,
-- c_FOUR_JC_TCK_C_LGTH = 7 for 1.25 MHz etc.
-- check also the c_JC_TIMEOUT_C_LGTH in the following paragraph
---------------------------------------------------------------------------------------------------
-- Constant regarding the session timeout counters --
---------------------------------------------------------------------------------------------------
-- To add a robust layer of protection to the FSMs of the desing, counters that depend only on
-- the system clock have being implemented; when they are filled up, they can bring the FSMs back
-- to the IDLE state.
-- For the wf_rx_deserializer, at the slowest bit rate, 31.25 kbps, the reception of the longest
-- frame should not last more than:
-- 133 bytes RP_DAT = 34048 us
-- This demands for a 21 bits counter.
-- Similarly, for the wf_tx_serializer, at the slowest bit rate, 31.25 kbps, the transmission of
-- the longest frame should not last more than:
-- 133 bytes RP_DAT = 34048 us
-- This demands for a 21 bits counter.
-- For the wf_engine_control, at the slowest bit rate, 31.25 kbps, the reception of an ID_DAT frame
-- followed by the reception/ transmission of an RP_DAT should not last more than:
-- 8 bytes ID_DAT = 2048 us
-- silence time = 4096 us
-- 133 bytes RP_DAT = 34048 us
-- ------------
-- 40192 us
-- This also demands for a 21 bits counter.
-- Therefore the same length of the timeout counters can be used for the FSMs of the wf_rx_deserializer,
-- wf_tx_serializer and wf_engine_control. The FSMs will be reset if 52 ms (complete 21 bit counter)
-- have passed since they have left the IDLE state.
constant c_SESSION_TIMEOUT_C_LGTH : natural := 21;
-- For the wf_jtag_controller FSM this timeout depends on the frequency of the JC_TCK.
-- The time the FSM needs to handle the biggest frame (122 bytes) is:
-- 122 * ((4 * JC_TCK_period) + 2 uclk_period)
-- For a 5 MHz JC_TCK this is 103.7 us and demands for a counter of 13 bits.
-- Use c_JC_TIMEOUT_C_LGTH = 13 also for a 2.5 MHz JC_TCK,
-- c_JC_TIMEOUT_C_LGTH = 14 for 1.25 MHz etc.
constant c_JC_TIMEOUT_C_LGTH : natural := 13;
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filter --
---------------------------------------------------------------------------------------------------
......@@ -135,20 +198,6 @@ package wf_package is
---------------------------------------------------------------------------------------------------
-- Constant regarding the JTAG controller --
---------------------------------------------------------------------------------------------------
constant c_MAX_FRAME_BITS : natural := 976; -- maximum number of TMS/ TDI bits that can be sent
-- in one frame : 122 bytes * 8 bits
constant c_FOUR_JC_TCK_C_LGTH : integer := 5; -- length of a counter counting 4 JC_TCK periods;
-- the JC_TCK frequency is defined by this constant.
-- ex: 5 MHz JC_TCK period = 200 ns = 4 uclk periods,
-- 4 JC_TCK periods = 16 uclk, hence 5 bits counter.
-- Use c_FOUR_JC_TCK_C_LGTH = 6 for a 2.5 MHz JC_TCK,
-- c_FOUR_JC_TCK_C_LGTH = 7 for 1.25 MHz etc.
---------------------------------------------------------------------------------------------------
-- Constant regarding the Model & Constructor decoding --
---------------------------------------------------------------------------------------------------
......
wf_prod_bytes_retriever.vhd
View file @ b1b865e3
......@@ -15,7 +15,7 @@
-- Description After an ID_DAT frame requesting for a variable to be produced, the unit provides |
-- to the wf_tx_serializer unit one by one, all the bytes of data needed for the |
-- RP_DAT frame (apart from the FSS, FCS and FES bytes). The coordination of the |
-- retreival is done through the wf_engine_control and the signal byte_index_i. |
-- retrieval is done through the wf_engine_control and the signal byte_index_i. |
-- |
-- General structure of a produced RP_DAT frame: |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
......@@ -214,12 +214,12 @@ begin
---------------------------------------------------------------------------------------------------
-- Memory mode Produced RAM --
-- Storage (by the user) & retreival (by the unit) of produced bytes --
-- Storage (by the user) & retrieval (by the unit) of produced bytes --
---------------------------------------------------------------------------------------------------
-- Instantiation of a 512 x 8 Produced Dual Port RAM.
-- Only 124 bytes of memory are used.
-- Port A is used by the nanoFIP for the readings from the Produced RAM;
-- Port B is connected to the WISHBONE interface for the writings from the user.
-- Note: only 124 bytes are used.
Produced_Bytes_From_RAM: wf_dualram_512x8_clka_rd_clkb_wr
port map(
......@@ -236,7 +236,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Slone mode DAT_I bus Sampling --
-- Retreival of the two bytes to be produced --
-- retrieval of the two bytes to be produced --
---------------------------------------------------------------------------------------------------
-- Sampling of the input data bus DAT_I(15:0) for the operation in stand-alone mode.
-- The sampling takes place on the 1st clock cycle after the VAR3_RDY has been de-asserted.
......@@ -329,7 +329,7 @@ begin
-- In memory mode:
if slone_i = '0' then
-- retreival of base address info for the memory from the wf_package
-- retrieval of base address info for the memory from the wf_package
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_addr;
......
wf_prod_data_lgth_calc.vhd
View file @ b1b865e3
......@@ -138,13 +138,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
-- data length information retrieval from the c_VARS_ARRAY matrix (wf_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
-- data length information retrieval from the c_VARS_ARRAY matrix (wf_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth;
......@@ -188,7 +188,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_5 =>
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
-- data length information retrieval from the c_VARS_ARRAY matrix (wf_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_5_INDEX).array_lgth;
......
wf_production.vhd
View file @ b1b865e3
......@@ -152,7 +152,7 @@ entity wf_production is port(
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);
-- used by: wf_prod_bytes_retriever for the bytes retreival in stand-alone mode
-- used by: wf_prod_bytes_retriever for the bytes retrieval in stand-alone mode
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
......@@ -171,7 +171,7 @@ entity wf_production is port(
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the wf_jtag_controller unit
jc_tdo_byte_i : in std_logic_vector (7 downto 0);
-- used by: wf_prod_bytes_retriever for the bytes retreival of a var_5
-- used by: wf_prod_bytes_retriever for the bytes retrieval of a var_5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -253,7 +253,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Bytes Retreival --
-- Bytes retrieval --
---------------------------------------------------------------------------------------------------
-- Instantiation of the wf_prod_bytes_retriever unit
......
wf_reset_unit.vhd
View file @ b1b865e3
......@@ -17,10 +17,10 @@
-- o nanoFIP internal reset that resets all nanoFIP's logic, apart from WISHBONE. |
-- It is asserted: |
-- - after the assertion of the "nanoFIP User Interface General signal" RSTIN; |
-- in this case it stays active for 2 uclk cycles |
-- in this case it stays active for 4 uclk cycles |
-- - after the reception of a var_rst with its 1st application-data byte |
-- containing the station's address; in this case as well it stays active for |
-- 2 uclk cycles |
-- 4 uclk cycles |
-- - during the activation of the "nanoFIP User Interface General signal" RSTPON;|
-- in this case it stays active for as long as the RSTPON is active. |
-- __________ |
......@@ -84,10 +84,11 @@
-- / / |
-- |
-- Notes: |
-- - The input signal RSTIN is considered only if it has been active for >8 uclk cycles|
-- - The input signal RSTIN is considered only if it has been active for at least |
-- 4 uclk cycles; the functional specs define 8 uclks, but in reality we check for 4.|
-- - The pulses rst_nFIP_and_FD_p and assert_RSTON_p come from the wf_cons_outcome |
-- unit only after the sucessful validation of the frame structure and of the |
-- application-data bytes of a var_rst. |
-- application-data bytes of the var_rst. |
-- - The RSTPON (Power On Reset generated with an RC circuit) removal is synchronized |
-- with both uclk and wb_clk. |
-- |
......@@ -105,12 +106,13 @@
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG checking of bytes1 and 2 of reset var added |
-- fd_rstn_o, nFIP_rst_o enabled only if rstin has been active for>4 uclk |
-- 01/2011 v0.03 EG PoR added; signals assert_RSTON_p_i & rst_nFIP_and_FD_p_i are inputs |
-- fd_rstn_o, nfip_rst_o enabled only if rstin has been active for>4 uclk |
-- 01/2011 v0.03 EG PoR added; signals assert_rston_p_i & rst_nfip_and_fd_p_i are inputs |
-- treated in the wf_cons_outcome; 2 state machines created; clean-up |
-- PoR also for internal WISHBONE resets |
-- 02/2011 v0.031 EG state nfip_off_fd_off added |
-- 02/2011 v0.031 EG state nFIP_OFF_FD_OFF added |
-- 11/2011 v0.032 EG added s_rstin_c_is_full, s_var_rst_c_is_full signals that reset FSMs |
-- corrections on # cycles nFIP_rst is activated (was 6, now 4) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -157,18 +159,18 @@ entity wf_reset_unit is port(
wb_clk_i : in std_logic; -- WISHBONE clock
-- Signal from the wf_consumption unit
rst_nFIP_and_FD_p_i : in std_logic; -- indicates that a var_rst with its 1st byte
rst_nfip_and_fd_p_i : in std_logic; -- indicates that a var_rst with its 1st byte
-- containing the station's address has been
-- correctly received
assert_RSTON_p_i : in std_logic; -- indicates that a var_rst with its 2nd byte
assert_rston_p_i : in std_logic; -- indicates that a var_rst with its 2nd byte
-- containing the station's address has been
-- correctly received
-- OUTPUTS
-- nanoFIP internal reset, to all the units
nFIP_rst_o : out std_logic; -- nanoFIP internal reset, active high
nfip_rst_o : out std_logic; -- nanoFIP internal reset, active high
-- resets all nanoFIP logic, apart from the WISHBONE
-- Signal to the wf_wb_controller
......@@ -192,23 +194,23 @@ architecture rtl of wf_reset_unit is
signal s_rsti_synch : std_logic_vector (2 downto 0);
signal s_wb_por_synch, s_u_por_synch : std_logic_vector (1 downto 0);
-- FSM for RSTIN
type rstin_st_t is (idle, rstin_eval, nfip_on_fd_on, nfip_off_fd_on, nfip_off_fd_off);
type rstin_st_t is (IDLE, RSTIN_EVAL, nFIP_ON_FD_ON, nFIP_OFF_FD_ON, nFIP_OFF_FD_OFF);
signal rstin_st, nx_rstin_st : rstin_st_t;
-- RSTIN counter
signal s_rstin_c, s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_four : std_logic;
signal s_rstin_c_is_ten, s_rstin_c_is_4txck : std_logic;
signal s_rstin_c_reinit, s_rstin_c_is_three : std_logic;
signal s_rstin_c_is_seven, s_rstin_c_is_4txck : std_logic;
signal s_rstin_c_is_full : std_logic;
-- resets generated after a RSTIN
signal s_rstin_nfip, s_rstin_fd : std_logic;
-- FSM for var_rst
type var_rst_st_t is (var_rst_idle, var_rst_rston_on, var_rst_nfip_on_fd_on_rston_on,
var_rst_nfip_off_fd_on_rston_on, var_rst_nfip_on_fd_on,
var_rst_nfip_off_fd_on_rston_off);
type var_rst_st_t is (VAR_RST_IDLE, VAR_RST_RSTON_ON, VAR_RST_nFIP_ON_FD_ON_RSTON_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_ON, VAR_RST_nFIP_ON_FD_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF);
signal var_rst_st, nx_var_rst_st : var_rst_st_t;
-- var_rst counter
signal s_var_rst_c_reinit, s_var_rst_c_is_two : std_logic;
signal s_var_rst_c_is_eight, s_var_rst_c_is_4txck : std_logic;
signal s_var_rst_c_reinit, s_var_rst_c_is_three : std_logic;
signal s_var_rst_c_is_seven, s_var_rst_c_is_4txck : std_logic;
signal s_var_rst_c_is_full : std_logic;
-- resets generated after a var_rst
signal s_var_rst_fd, s_var_rst_nfip, s_rston : std_logic;
......@@ -237,7 +239,7 @@ begin
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTIN synchronization with a set of 3 registers.
-- RSTIN synchronization with the uclk, using a set of 3 registers.
RSTIN_uclk_Synchronizer: process (uclk_i)
begin
......@@ -248,7 +250,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronization of the Power On Reset removal, with the wb_clk.
-- RSTPON synchronization, with the wb_clk.
-- The second flip-flop is used to remove metastabilities.
PoR_wb_clk_Synchronizer: process (wb_clk_i, rstpon_a_i)
......@@ -262,7 +264,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronization of the Power On Reset removal, with the uclk.
-- RSTPON synchronization, with the uclk.
-- The second flip-flop is used to remove metastabilities.
PoR_uclk_Synchronizer: process (uclk_i, rstpon_a_i)
......@@ -286,11 +288,11 @@ begin
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- The FSM is following the "User Interface, General signal" RSTIN and checks whether it stays
-- active for at least 4 uclk cycles; if so, it enables the nanoFIP internal reset (s_rstin_nfip)
-- and the FIELDRIVE reset (s_rstin_fd). The nanoFIP internal reset stays active for 4 uclk cycles
-- and the FIELDRIVE for 4 FD_TXCK cycles.
-- The state machine can be reset by the Power On Reset and the variable reset.
-- and the FIELDRIVE for 4 FD_TXCK cycles.
-- Note: The same counter is used for the evaluation of the RSTIN (if it is >= 4 uclk) and for the
-- generation of the two reset signals.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -299,8 +301,8 @@ begin
RSTIN_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por_synch(1) = '1' or rst_nFIP_and_FD_p_i = '1' or s_rstin_c_is_full = '1' then
rstin_st <= idle;
if s_u_por_synch(1) = '1' or rst_nfip_and_fd_p_i = '1' or s_rstin_c_is_full = '1' then
rstin_st <= IDLE;
else
rstin_st <= nx_rstin_st;
end if;
......@@ -312,68 +314,68 @@ begin
-- Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
-- transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, s_rsti_synch(2), s_rstin_c_is_four,
s_rstin_c_is_ten, s_rstin_c_is_4txck)
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, s_rsti_synch(2), s_rstin_c_is_three,
s_rstin_c_is_seven, s_rstin_c_is_4txck)
begin
case rstin_st is
when idle =>
when IDLE =>
if s_rsti_synch(2) = '1' then -- RSTIN active
nx_rstin_st <= rstin_eval;
nx_rstin_st <= RSTIN_EVAL;
else
nx_rstin_st <= idle;
nx_rstin_st <= IDLE;
end if;
when rstin_eval =>
when RSTIN_EVAL =>
if s_rsti_synch(2) = '0' then -- RSTIN deactivated
nx_rstin_st <= idle;
nx_rstin_st <= IDLE;
else
if s_rstin_c_is_four = '1' then -- counting the uclk cycles that
nx_rstin_st <= nfip_on_fd_on; -- RSTIN is active
if s_rstin_c_is_three = '1' then -- counting the uclk cycles that
nx_rstin_st <= nFIP_ON_FD_ON; -- RSTIN is active
else
nx_rstin_st <= rstin_eval;
nx_rstin_st <= RSTIN_EVAL;
end if;
end if;
when nfip_on_fd_on =>
when nFIP_ON_FD_ON =>
if s_rstin_c_is_ten = '1' then -- nanoFIP internal reset and
nx_rstin_st <= nfip_off_fd_on; -- FIELDRIVE reset active for
-- 2 uclk cycles
if s_rstin_c_is_seven = '1' then -- nanoFIP internal reset and
nx_rstin_st <= nFIP_OFF_FD_ON; -- FIELDRIVE reset active for
-- 4 uclk cycles
else
nx_rstin_st <= nfip_on_fd_on;
nx_rstin_st <= nFIP_ON_FD_ON;
end if;
when nfip_off_fd_on =>
when nFIP_OFF_FD_ON =>
-- nanoFIP internal reset deactivated
if s_rstin_c_is_4txck = '1' then -- FIELDRIVE reset continues being active
nx_rstin_st <= nfip_off_fd_off;-- unitl 4 FD_TXCK cycles have passed
nx_rstin_st <= nFIP_OFF_FD_OFF;-- until 4 FD_TXCK cycles have passed
else
nx_rstin_st <= nfip_off_fd_on;
nx_rstin_st <= nFIP_OFF_FD_ON;
end if;
when nfip_off_fd_off =>
when nFIP_OFF_FD_OFF =>
if s_rsti_synch(2) = '1' then -- RSTIN still active
nx_rstin_st <= nfip_off_fd_off;
nx_rstin_st <= nFIP_OFF_FD_OFF;
else
nx_rstin_st <= idle;
nx_rstin_st <= IDLE;
end if;
when others =>
nx_rstin_st <= idle;
when OTHERS =>
nx_rstin_st <= IDLE;
end case;
end process;
......@@ -388,22 +390,22 @@ begin
case rstin_st is
when idle =>
when IDLE =>
s_rstin_c_reinit <= '1'; -- counter initialized
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when rstin_eval =>
when RSTIN_EVAL =>
s_rstin_c_reinit <= '0'; -- counting until 4
-- if RSTIN is active
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when nfip_on_fd_on =>
s_rstin_c_reinit <= '0'; -- free counter counting 2 uclk cycles
when nFIP_ON_FD_ON =>
s_rstin_c_reinit <= '0'; -- free counter counting 4 uclk cycles
-------------------------------------
s_rstin_fd <= '1'; -- FIELDRIVE active
......@@ -411,8 +413,8 @@ begin
-------------------------------------
when nfip_off_fd_on =>
s_rstin_c_reinit <= '0'; -- free counter counting 4 FD_TXCK cycles
when nFIP_OFF_FD_ON =>
s_rstin_c_reinit <= '0'; -- free counter counting until 4 FD_TXCK
s_rstin_nfip <= '0';
-------------------------------------
......@@ -420,14 +422,14 @@ begin
-------------------------------------
when nfip_off_fd_off =>
when nFIP_OFF_FD_OFF =>
s_rstin_c_reinit <= '1'; -- no counting
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when others =>
when OTHERS =>
s_rstin_c_reinit <= '1'; -- no counting
s_rstin_fd <= '0';
......@@ -455,9 +457,10 @@ RSTIN_free_counter: wf_incr_counter
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_rstin_c_is_four <= '1' when s_rstin_c = to_unsigned(4, s_rstin_c'length) else '0';
s_rstin_c_is_ten <= '1' when s_rstin_c = to_unsigned(10, s_rstin_c'length) else '0';
s_rstin_c_is_4txck <= '1' when s_rstin_c = s_txck_four_periods else '0';
s_rstin_c_is_three <= '1' when s_rstin_c = to_unsigned(3, s_rstin_c'length) else '0';
s_rstin_c_is_seven <= '1' when s_rstin_c = to_unsigned(7, s_rstin_c'length) else '0';
s_rstin_c_is_4txck <= '1' when s_rstin_c = s_txck_four_periods + 3 else '0';
-- +3 bc of the first 4 RSTIN evaluation cycles
......@@ -467,12 +470,12 @@ RSTIN_free_counter: wf_incr_counter
-- Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- If after the reception of a var_rst the signal assert_RSTON_p_i is asserted, the FSM
-- If after the reception of a var_rst the signal assert_rston_p_i is asserted, the FSM
-- asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
-- If after the reception of a var_rst the signal rst_nFIP_and_FD_p_i is asserted, the FSM
-- asserts the nanoFIP internal reset (s_var_rst_nfip) for 2 uclk cycles and the
-- If after the reception of a var_rst the signal rst_nfip_and_fd_p_i is asserted, the FSM
-- asserts the nanoFIP internal reset (s_var_rst_nfip) for 4 uclk cycles and the
-- "nanoFIP FIELDRIVE" output (s_var_rst_fd) for 4 FD_TXCK cycles.
-- If after the reception of a var_rst both assert_RSTON_p_i and rst_nFIP_and_FD_p_i
-- If after the reception of a var_rst both assert_rston_p_i and rst_nfip_and_fd_p_i
-- are asserted, the FSM asserts the s_var_rst_nfip for 2 uclk cycles, the RSTON for 8
-- uclk cycles and the s_var_rst_fd for 4 FD_TXCK cycles.
-- The same counter is used for all the countings!
......@@ -483,8 +486,8 @@ RSTIN_free_counter: wf_incr_counter
Resets_after_a_var_rst_synch: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por_synch(1) = '1' or s_rstin_nfip = '1' then
var_rst_st <= var_rst_idle;
if s_u_por_synch(1) = '1' or s_rstin_nfip = '1' or s_var_rst_c_is_full = '1' then
var_rst_st <= VAR_RST_IDLE;
else
var_rst_st <= nx_var_rst_st;
end if;
......@@ -496,83 +499,83 @@ RSTIN_free_counter: wf_incr_counter
-- Combinatorial process Resets_after_a_var_rst_Comb_State_Transitions: definition of the
-- state transitions of the FSM.
Resets_after_a_var_rst_Comb_State_Transitions: process (var_rst_st, rst_nFIP_and_FD_p_i,
assert_RSTON_p_i, s_var_rst_c_is_two,
s_var_rst_c_is_eight,
Resets_after_a_var_rst_Comb_State_Transitions: process (var_rst_st, rst_nfip_and_fd_p_i,
assert_rston_p_i, s_var_rst_c_is_three,
s_var_rst_c_is_seven,
s_var_rst_c_is_4txck)
begin
case var_rst_st is
when var_rst_idle =>
when VAR_RST_IDLE =>
if assert_RSTON_p_i = '1' and rst_nFIP_and_FD_p_i = '1' then
nx_var_rst_st <= var_rst_nfip_on_fd_on_rston_on;
if assert_rston_p_i = '1' and rst_nfip_and_fd_p_i = '1' then
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON_RSTON_ON;
elsif assert_RSTON_p_i = '1' then
nx_var_rst_st <= var_rst_rston_on;
elsif assert_rston_p_i = '1' then
nx_var_rst_st <= VAR_RST_RSTON_ON;
elsif rst_nFIP_and_FD_p_i = '1' then
nx_var_rst_st <= var_rst_nfip_on_fd_on;
elsif rst_nfip_and_fd_p_i = '1' then
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON;
else
nx_var_rst_st <= var_rst_idle;
nx_var_rst_st <= VAR_RST_IDLE;
end if;
when var_rst_rston_on => -- for 8 uclk cycles
when VAR_RST_RSTON_ON => -- for 8 uclk cycles
if s_var_rst_c_is_eight = '1' then
nx_var_rst_st <= var_rst_idle;
if s_var_rst_c_is_seven = '1' then
nx_var_rst_st <= VAR_RST_IDLE;
else
nx_var_rst_st <= var_rst_rston_on;
nx_var_rst_st <= VAR_RST_RSTON_ON;
end if;
when var_rst_nfip_on_fd_on_rston_on => -- for 2 uclk cycles
when VAR_RST_nFIP_ON_FD_ON_RSTON_ON => -- for 4 uclk cycles
if s_var_rst_c_is_two = '1' then
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_on;
if s_var_rst_c_is_three = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_ON;
else
nx_var_rst_st <= var_rst_nfip_on_fd_on_rston_on;
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON_RSTON_ON;
end if;
when var_rst_nfip_off_fd_on_rston_on => -- for 6 uclk cycles
when VAR_RST_nFIP_OFF_FD_ON_RSTON_ON => -- for 4 more uclk cycles
if s_var_rst_c_is_eight = '1' then
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_off;
if s_var_rst_c_is_seven = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
else
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_on;
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_ON;
end if;
when var_rst_nfip_on_fd_on => -- for 2 uclk cycles
when VAR_RST_nFIP_ON_FD_ON => -- for 4 uclk cycles
if s_var_rst_c_is_two = '1' then
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_off;
if s_var_rst_c_is_three = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
else
nx_var_rst_st <= var_rst_nfip_on_fd_on;
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON;
end if;
when var_rst_nfip_off_fd_on_rston_off => -- until the filling-up of the counter
when VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF => -- until 4 TXCK
if s_var_rst_c_is_4txck = '1' then
nx_var_rst_st <= var_rst_idle;
nx_var_rst_st <= VAR_RST_IDLE;
else
nx_var_rst_st <= var_rst_nfip_off_fd_on_rston_off;
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
end if;
when others =>
nx_var_rst_st <= var_rst_idle;
when OTHERS =>
nx_var_rst_st <= VAR_RST_IDLE;
end case;
end process;
......@@ -587,7 +590,7 @@ RSTIN_free_counter: wf_incr_counter
case var_rst_st is
when var_rst_idle =>
when VAR_RST_IDLE =>
s_var_rst_c_reinit <= '1'; -- counter initialized
s_rston <= '1';
......@@ -595,7 +598,7 @@ RSTIN_free_counter: wf_incr_counter
s_var_rst_fd <= '0';
when var_rst_rston_on =>
when VAR_RST_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 8 uclk cycles
-------------------------------------
......@@ -605,8 +608,8 @@ RSTIN_free_counter: wf_incr_counter
s_var_rst_fd <= '0';
when var_rst_nfip_on_fd_on_rston_on =>
s_var_rst_c_reinit <= '0'; -- counting 2 uclk cycles
when VAR_RST_nFIP_ON_FD_ON_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
-------------------------------------
s_rston <= '0'; -- RSTON active
......@@ -615,8 +618,8 @@ RSTIN_free_counter: wf_incr_counter
-------------------------------------
when var_rst_nfip_off_fd_on_rston_on =>
s_var_rst_c_reinit <= '0'; -- counting 6 uclk cycles
when VAR_RST_nFIP_OFF_FD_ON_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
s_var_rst_nfip <= '0';
-------------------------------------
......@@ -625,8 +628,8 @@ RSTIN_free_counter: wf_incr_counter
-------------------------------------
when var_rst_nfip_on_fd_on =>
s_var_rst_c_reinit <= '0'; -- counting 2 uclk cycles
when VAR_RST_nFIP_ON_FD_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
s_rston <= '1';
-------------------------------------
......@@ -635,8 +638,8 @@ RSTIN_free_counter: wf_incr_counter
-------------------------------------
when var_rst_nfip_off_fd_on_rston_off =>
s_var_rst_c_reinit <= '0'; -- counting 4 FD_TXCK cycles
when VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF =>
s_var_rst_c_reinit <= '0'; -- counting until 4 FD_TXCK cycles
s_rston <= '1';
s_var_rst_nfip <= '0';
......@@ -645,7 +648,7 @@ RSTIN_free_counter: wf_incr_counter
-------------------------------------
when others =>
when OTHERS =>
s_var_rst_c_reinit <= '1'; -- no counting
s_rston <= '1';
......@@ -661,7 +664,9 @@ RSTIN_free_counter: wf_incr_counter
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter:
-- the counter counts from 0 to 8, if only assert_RSTON_p has been activated, or
-- from 0 to 4 * FD_TXCK, if rst_nFIP_and_FD_p has been activated.
-- from 0 to 4 * FD_TXCK, if rst_nfip_and_fd_p_i has been activated.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
-- s_var_rst_c_is_full will be activated and the FSM will be reset.
free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
......@@ -675,9 +680,9 @@ free_counter: wf_incr_counter
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_c_is_eight <= '1' when s_var_rst_c= to_unsigned(8, s_var_rst_c'length) else '0';
s_var_rst_c_is_two <= '1' when s_var_rst_c= to_unsigned(2, s_var_rst_c'length) else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c= s_txck_four_periods else '0';
s_var_rst_c_is_seven <= '1' when s_var_rst_c = to_unsigned(7, s_var_rst_c'length) else '0';
s_var_rst_c_is_three <= '1' when s_var_rst_c = to_unsigned(3, s_var_rst_c'length) else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_four_periods -1 else '0';
......@@ -689,7 +694,7 @@ free_counter: wf_incr_counter
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
nFIP_rst_o <= s_rstin_nfip or s_var_rst_nfip or s_u_por_synch(1);
nfip_rst_o <= s_rstin_nfip or s_var_rst_nfip or s_u_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......
wf_rx_deglitcher.vhd
View file @ b1b865e3
......@@ -121,7 +121,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Deglitching --
-- Deglitching --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
......
wf_rx_deserializer.vhd
View file @ b1b865e3
......@@ -74,7 +74,7 @@
-- like this we confirm that the CRC_ok_p arrived just before the FES, |
-- and any 2 bytes that could by chanche be seen as CRC, are neglected. |
-- FSM data_field_byte state: redundant code removed: |
-- "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle" |
-- "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then IDLE" |
-- code(more!)cleaned-up |
-- 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if |
-- bytes with size different than 8 have preceeded. |
......@@ -173,8 +173,8 @@ end entity wf_rx_deserializer;
architecture rtl of wf_rx_deserializer is
-- FSM
type rx_st_t is (idle, pre_field_first_f_edge, pre_field_r_edge, pre_field_f_edge, fsd_field,
ctrl_data_fcs_fes_fields);
type rx_st_t is (IDLE, PRE_FIELD_FIRST_F_EDGE, PRE_FIELD_R_EDGE, PRE_FIELD_F_EDGE, FSD_FIELD,
CTRL_DATA_FCS_FES_FIELDS);
signal rx_st, nx_rx_st : rx_st_t;
signal s_idle, s_receiving_pre, s_receiving_fsd, s_receiving_bytes : std_logic;
-- PRE detection
......@@ -189,7 +189,7 @@ architecture rtl of wf_rx_deserializer is
signal s_byte : std_logic_vector (7 downto 0);
-- CRC calculation
signal s_CRC_ok_p, s_CRC_ok_p_d, s_CRC_ok_p_found : std_logic;
-- independant timeout counter
-- independent timeout counter
signal s_session_timedout : std_logic;
......@@ -212,14 +212,14 @@ begin
-- A robust protection, that depends only on the system clock, has been implemented:
-- knowing that at any bit rate the reception of a frame should not last more than 35ms (this
-- corresponds to the consumption of 133 bytes at 31.25 Kbps), a counter has been implemented,
-- responsible for bringing the machine back to idle if more than 52ms (complete 21 bit counter)
-- have passed since the machine left the idle state.
-- responsible for bringing the machine back to IDLE if more than 52ms (complete 21 bit counter)
-- have passed since the machine left the IDLE state.
Deserializer_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or rx_rst_i = '1' or s_session_timedout = '1' then
rx_st <= idle;
rx_st <= IDLE;
else
rx_st <= nx_rx_st;
end if;
......@@ -242,101 +242,101 @@ begin
-- During the PRE, the wf_rx_osc is trying to synchronize to the transmitter's clock and every
-- edge detected in the FD_RXD is taken into account. At this phase, the unit uses
-- the wf_rx_osc signals: adjac_bits_window_i and signif_edge_window_i and if edges are found
-- outside those windows the unit goes back to idle and the wf_rx_osc is reset.
-- outside those windows the unit goes back to IDLE and the wf_rx_osc is reset.
-- For the rest of the frame, the unit is just sampling the deglitched FD_RXD on the moments
-- specified by the wf_rx_osc signals: sample_manch_bit_p_i and sample_bit_p_i.
when idle =>
when IDLE =>
if fd_rxd_f_edge_p_i = '1' then -- falling edge detection
nx_rx_st <= pre_field_first_f_edge;
nx_rx_st <= PRE_FIELD_FIRST_F_EDGE;
else
nx_rx_st <= idle;
nx_rx_st <= IDLE;
end if;
when pre_field_first_f_edge =>
when PRE_FIELD_FIRST_F_EDGE =>
if s_manch_r_edge_p = '1' then -- arrival of a manch.
nx_rx_st <= pre_field_r_edge; -- rising edge
nx_rx_st <= PRE_FIELD_R_EDGE; -- rising edge
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
nx_rx_st <= IDLE;
else
nx_rx_st <= pre_field_first_f_edge;
nx_rx_st <= PRE_FIELD_FIRST_F_EDGE;
end if;
when pre_field_r_edge =>
when PRE_FIELD_R_EDGE =>
if s_manch_f_edge_p = '1' then -- arrival of a manch. falling edge
nx_rx_st <= pre_field_f_edge; -- note: several loops between
nx_rx_st <= PRE_FIELD_F_EDGE; -- note: several loops between
-- a rising and a falling edge are
-- expected for the PRE
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
nx_rx_st <= IDLE;
else
nx_rx_st <= pre_field_r_edge;
nx_rx_st <= PRE_FIELD_R_EDGE;
end if;
when pre_field_f_edge =>
when PRE_FIELD_F_EDGE =>
if s_manch_r_edge_p = '1' then -- arrival of a manch. rising edge
nx_rx_st <= pre_field_r_edge;
nx_rx_st <= PRE_FIELD_R_EDGE;
elsif s_bit_r_edge_p = '1' then -- arrival of a rising edge between
nx_rx_st <= fsd_field; -- adjacent bits, signaling the
nx_rx_st <= FSD_FIELD; -- adjacent bits, signaling the
-- beginning of the 1st V+ violation
-- of the FSD
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
nx_rx_st <= IDLE;
else
nx_rx_st <= pre_field_f_edge;
nx_rx_st <= PRE_FIELD_F_EDGE;
end if;
-- For the monitoring of the FSD, the unit is sampling each manch. bit of the incoming
-- FD_RXD and it is comparing it to the nominal bit of the FSD; the signal s_fsd_wrong_bit
-- is doing this comparison. If a wrong bit is received, the state machine jumps back to idle,
-- whereas if the complete byte is correctly received, it jumps to the ctrl_data_fcs_fes_fields.
-- is doing this comparison. If a wrong bit is received, the state machine jumps back to IDLE,
-- whereas if the complete byte is correctly received, it jumps to the CTRL_DATA_FCS_FES_FIELDS.
when fsd_field =>
when FSD_FIELD =>
if s_fsd_last_bit = '1' then -- reception of the last (15th)
nx_rx_st <= ctrl_data_fcs_fes_fields;-- FSD bit
nx_rx_st <= CTRL_DATA_FCS_FES_FIELDS;-- FSD bit
elsif s_fsd_wrong_bit = '1' then -- wrong bit
nx_rx_st <= idle;
nx_rx_st <= IDLE;
else
nx_rx_st <= fsd_field;
nx_rx_st <= FSD_FIELD;
end if;
-- The state machine stays in the ctrl_data_fcs_fes_fields state until a FES detection (or
-- The state machine stays in the CTRL_DATA_FCS_FES_FIELDS state until a FES detection (or
-- a reset rx_rst_i signal or a s_session_timeout signal). In this state bytes are "blindly"
-- being constructed and it is the wf_engine_control unit that supervises what is being received;
-- if for example an ID_DAT is being received without a FES detected after 8 bytes or an
-- RP_DAT without a FES after 133 bytes, or if the CTRL byte of an ID_DAT is wrong, the
-- engine_control will discard the current reception and reset the FSM through the rx_rst_i.
when ctrl_data_fcs_fes_fields =>
when CTRL_DATA_FCS_FES_FIELDS =>
if s_fes_detected = '1' then
nx_rx_st <= idle;
nx_rx_st <= IDLE;
else
nx_rx_st <= ctrl_data_fcs_fes_fields;
nx_rx_st <= CTRL_DATA_FCS_FES_FIELDS;
end if;
when others =>
nx_rx_st <= idle;
when OTHERS =>
nx_rx_st <= IDLE;
end case;
end process;
......@@ -351,7 +351,7 @@ begin
case rx_st is
when idle =>
when IDLE =>
------------------------------------
s_idle <= '1';
------------------------------------
......@@ -360,7 +360,7 @@ begin
s_receiving_bytes <= '0';
when pre_field_first_f_edge | pre_field_r_edge | pre_field_f_edge =>
when PRE_FIELD_FIRST_F_EDGE | PRE_FIELD_R_EDGE | PRE_FIELD_F_EDGE =>
s_idle <= '0';
------------------------------------
......@@ -370,7 +370,7 @@ begin
s_receiving_bytes <= '0';
when fsd_field =>
when FSD_FIELD =>
s_idle <= '0';
s_receiving_pre <= '0';
......@@ -380,7 +380,7 @@ begin
s_receiving_bytes <= '0';
when ctrl_data_fcs_fes_fields =>
when CTRL_DATA_FCS_FES_FIELDS =>
s_idle <= '0';
s_receiving_pre <= '0';
......@@ -390,9 +390,11 @@ begin
------------------------------------
when others =>
when OTHERS =>
s_idle <= '0';
------------------------------------
s_idle <= '1';
------------------------------------
s_receiving_pre <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
......@@ -408,13 +410,14 @@ begin
-- Synchronous process Append_Bit_To_Byte: Creation of bytes of data.
-- A new bit of the FD_RXD is appended to the output byte that is being formed when the FSM is in
-- the "ctrl_data_fcs_fes_fields" state, on the "sample_bit_p_i" moments.
-- the "CTRL_DATA_FCS_FES_FIELDS" state, on the "sample_bit_p_i" moments.
Append_Bit_To_Byte: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_byte_ready_p_d1 <='0';
s_byte_ready_p_d1 <= '0';
s_sample_manch_bit_p_d1 <= '0';
s_byte <= (others => '0');
else
......@@ -532,7 +535,7 @@ begin
CRC_OK_pulse_delay: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_receiving_bytes = '0' then
if nfip_rst_i = '1' or s_receiving_bytes = '0' then
s_CRC_ok_p_d <= '0';
s_CRC_ok_p_found <= '0';
else
......@@ -561,11 +564,11 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_decr_counter relying only on the system clock, as an additional
-- way to go back to Idle state, in case any other logic is being stuck. The length of the counter
-- is defined using the slowest bit rate and considering reception of the upper limit of 134 bytes.
-- way to go back to IDLE state, in case any other logic is being stuck. The length of the counter
-- is defined using the slowest bit rate and considering reception of the upper limit of 133 bytes.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => 21)
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
......
wf_status_bytes_gen.vhd
View file @ b1b865e3
......@@ -90,6 +90,8 @@
-- var_i added for the jtag_var1 treatment; |
-- r_fcser, r_tler_o considered only for a cons variable (bf a wrong |
-- crc on an id-dat could give r_fcser) |
-- 11/2011 v0.042 EG the var3_acc_a_i and not the s_var3_acc_synch(3) was used for |
-- the refreshment:s |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -253,7 +255,7 @@ begin
if rst_status_bytes_p_i = '1' then -- bit reinitialized after a production
s_refreshment <= '0';
elsif var3_acc_a_i = '1' then -- indication that the memory has been accessed
elsif s_var3_acc_synch(2) = '1' then -- indication that the memory has been accessed
s_refreshment <= '1';
end if;
......
wf_tx_serializer.vhd
View file @ b1b865e3
......@@ -42,8 +42,8 @@
-- v0.03 07/2010 EG timing changes; tx_sched_p_buff_i got 1 more bit |
-- briefly byte_index_i needed to arrive 1 clock tick earlier |
-- renamed from tx to tx_serializer; |
-- stop_transmission state added for the synch of txena |
-- v0.04 01/2011 EG sync_to_txck state added to start always with the bits 1,2,3 of the |
-- STOP_TRANSMISSION state added for the synch of txena |
-- v0.04 01/2011 EG SYNC_TO_TXCK state added to start always with the bits 1,2,3 of the |
-- clock buffer available(tx_start_p_i may arrive at any time) |
-- tx_completed_p_o signal added |
-- v0.05 07/2011 EG bits_to_txd unit removed |
......@@ -125,8 +125,8 @@ end entity wf_tx_serializer;
architecture rtl of wf_tx_serializer is
-- FSM
type tx_st_t is (idle, sync_to_txck, send_fss, send_data_byte,
send_crc_bytes, send_fes, stop_transmission);
type tx_st_t is (IDLE, SYNC_TO_TXCK, SEND_FSS, SEND_DATA_BYTE,
SEND_CRC_BYTES, SEND_FES, STOP_TRANSMISSION);
signal tx_st, nx_tx_st : tx_st_t;
signal s_prepare_to_produce, s_sending_fss, s_sending_data : std_logic;
signal s_sending_crc, s_sending_fes, s_stop_transmission : std_logic;
......@@ -142,7 +142,7 @@ architecture rtl of wf_tx_serializer is
signal s_start_crc_p, s_data_bit_to_crc_p : std_logic;
signal s_crc_bytes : std_logic_vector (15 downto 0);
signal s_crc_bytes_manch : std_logic_vector (31 downto 0);
-- independant timeout counter
-- independent timeout counter
signal s_session_timedout : std_logic;
......@@ -180,19 +180,19 @@ begin
-- and when the Outgoing_Bits_Index counter is empty (which means that the last bit of a previous
-- byte is now being delivered).
-- The wf_engine_control responds to the request by sending a new address to the wf_production
-- for the retreival of a byte from the memory or the stand-alone bus.
-- for the retrieval of a byte from the memory or the stand-alone bus.
-- The byte becomes available at the byte_request_accept_p_i pulse, 2 cycles after the request,
-- and starts being transmitted at the tx_sched_p_buff (1) of the next FD_TXCK cycle.
-- The wf_engine_control is the one keeping track of the amount of bytes delivered and asserts
-- the last_byte_p_i signal accordingly; after the arrival of this signal the serializer's FSM
-- proceeds with the transmission of the CRC and the FES bytes and then goes back to idle.
-- proceeds with the transmission of the CRC and the FES bytes and then goes back to IDLE.
-- To add a rubust layer of protection to the FSM, we have implemented a counter, dependant only
-- on the system clock, that from any state can bring the FSM back to idle. At any bit rate the
-- To add a robust layer of protection to the FSM, we have implemented a counter, dependent only
-- on the system clock, that from any state can bring the FSM back to IDLE. At any bit rate the
-- transmission of the longest RP_DAT should not last more than 35ms. Hence, we have generated a
-- 21 bits counter that will reset the machine if more than 52ms (complete 21 bit counter) have
-- passed since it has left this idle state.
-- 21 bits (c_SESSION_TIMEOUT_C_LGTH) counter that will reset the machine if more than 52ms
-- (complete 21 bit counter) have passed since it has left this IDLE state.
---------------------------------------------------------------------------------------------------
-- Serializer's FSM --
......@@ -209,7 +209,7 @@ begin
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_session_timedout = '1' then
tx_st <= idle;
tx_st <= IDLE;
else
tx_st <= nx_tx_st;
end if;
......@@ -225,79 +225,79 @@ begin
case tx_st is
when idle =>
when IDLE =>
if tx_start_p_i = '1' then -- trigger from wf_engine_control
nx_tx_st <= sync_to_txck;
nx_tx_st <= SYNC_TO_TXCK;
else
nx_tx_st <= idle;
nx_tx_st <= IDLE;
end if;
when sync_to_txck => -- synch to the free running FD_TXTCK
when SYNC_TO_TXCK => -- synch to the free running FD_TXTCK
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-4) = '1' then
nx_tx_st <= send_fss;
nx_tx_st <= SEND_FSS;
else
nx_tx_st <= sync_to_txck;
nx_tx_st <= SYNC_TO_TXCK;
end if;
when send_fss => -- delivery of 2 FSS bytes
when SEND_FSS => -- delivery of 2 FSS bytes
if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) = '1') then
nx_tx_st <= send_data_byte;
nx_tx_st <= SEND_DATA_BYTE;
else
nx_tx_st <= send_fss;
nx_tx_st <= SEND_FSS;
end if;
when send_data_byte => -- delivery of several data bytes
when SEND_DATA_BYTE => -- delivery of several data bytes
-- until the last_byte_p_i notification
if last_byte_p_i = '1' then
nx_tx_st <= send_crc_bytes;
nx_tx_st <= SEND_CRC_BYTES;
else
nx_tx_st <= send_data_byte;
nx_tx_st <= SEND_DATA_BYTE;
end if;
when send_crc_bytes => -- delivery of 2 CRC bytes
when SEND_CRC_BYTES => -- delivery of 2 CRC bytes
if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then
nx_tx_st <= send_fes; -- state change early enough (tx_sched_p_buff_i(2))
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_sched_p_buff_i(3), to get the 31 as top value
nx_tx_st <= SEND_FES; -- state change early enough (tx_sched_p_buff_i(2))
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_sched_p_buff_i(3), to get the 31 as top value
else
nx_tx_st <= send_crc_bytes;
nx_tx_st <= SEND_CRC_BYTES;
end if;
when send_fes => -- delivery of 1 FES byte
when SEND_FES => -- delivery of 1 FES byte
if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then
nx_tx_st <= stop_transmission; -- state change early enough (tx_sched_p_buff_i(2))
nx_tx_st <= STOP_TRANSMISSION; -- state change early enough (tx_sched_p_buff_i(2))
-- for the Outgoing_Bits_Index that is loaded on
-- tx_sched_p_buff_i(3) to get the 15 as top value
else
nx_tx_st <= send_fes;
nx_tx_st <= SEND_FES;
end if;
when stop_transmission =>
when STOP_TRANSMISSION =>
-- end of transmission synchronous to the FD_TXCK
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1' then
nx_tx_st <= idle;
nx_tx_st <= IDLE;
else
nx_tx_st <= stop_transmission;
nx_tx_st <= STOP_TRANSMISSION;
end if;
when others =>
nx_tx_st <= idle;
when OTHERS =>
nx_tx_st <= IDLE;
end case;
end process;
......@@ -310,7 +310,7 @@ begin
case tx_st is
when idle | sync_to_txck =>
when IDLE | SYNC_TO_TXCK =>
---------------------------------
s_prepare_to_produce <= '1';
......@@ -322,7 +322,7 @@ begin
s_stop_transmission <= '0';
when send_fss =>
when SEND_FSS =>
s_prepare_to_produce <= '0';
---------------------------------
......@@ -334,7 +334,7 @@ begin
s_stop_transmission <= '0';
when send_data_byte =>
when SEND_DATA_BYTE =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
......@@ -346,7 +346,7 @@ begin
s_stop_transmission <= '0';
when send_crc_bytes =>
when SEND_CRC_BYTES =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
......@@ -358,7 +358,7 @@ begin
s_stop_transmission <= '0';
when send_fes =>
when SEND_FES =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
......@@ -370,7 +370,7 @@ begin
s_stop_transmission <= '0';
when stop_transmission =>
when STOP_TRANSMISSION =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
......@@ -382,14 +382,16 @@ begin
---------------------------------
when others =>
when OTHERS =>
s_prepare_to_produce <= '0';
s_sending_fss <= '0';
s_sending_data <= '0';
s_sending_crc <= '0';
s_sending_fes <= '0';
s_stop_transmission <= '0';
---------------------------------
s_prepare_to_produce <= '1';
---------------------------------
s_sending_fss <= '0';
s_sending_data <= '0';
s_sending_crc <= '0';
s_sending_fes <= '0';
s_stop_transmission <= '0';
end case;
......@@ -540,7 +542,7 @@ Input_Byte_Retrieval: process (uclk_i)
---------------------------------------------------------------------------------------------------
-- Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
-- same moment as the first bit of the PRE starts being delivered and stays asserted until the
-- same moment as the first bit of the FSS starts being delivered and stays asserted until the
-- end of the delivery of the last FES bit.
FD_TXENA_Generator: process (uclk_i)
......@@ -551,8 +553,8 @@ Input_Byte_Retrieval: process (uclk_i)
else
if ((s_sending_fss = '1') or (s_sending_data = '1') or -- tx sending bits
(s_sending_crc = '1') or (s_sending_fes = '1') or (s_stop_transmission = '1')) then
if ((s_sending_fss = '1') or (s_sending_data = '1') or (s_sending_crc = '1') or
(s_sending_fes = '1') or (s_stop_transmission = '1')) then -- tx sending bits
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then
-- in order to synchronise the
......@@ -578,10 +580,10 @@ Input_Byte_Retrieval: process (uclk_i)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_decr_counter relying only on the system clock as an additional
-- way to go back to Idle state, in case any other logic is being stuck.
-- way to go back to IDLE state, in case any other logic is being stuck.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => 21)
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
......
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