JTAG_contoller: added a counter for the bits that are being played to avoid…

JTAG_contoller: added a counter for the bits that are being played to avoid complicated combinatorial calculations git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@231 7f0067c9-7624-46c7-bd39-3fb5400c0213

JTAG_contoller: added a counter for the bits that are being played to avoid…
JTAG_contoller: added a counter for the bits that are being played to avoid complicated combinatorial calculations git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@231 7f0067c9-7624-46c7-bd39-3fb5400c0213
a1350268 · egousiou · e91158c9 · a1350268 · a1350268 · a1350268
Commit a1350268 authored Sep 07, 2011 by egousiou
6 changed files
--- a/DualClkRAM.vhd
+++ b/DualClkRAM.vhd
@@ -53,9 +53,9 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
 use IEEE.NUMERIC_STD.all;    -- conversion functions
-- Specific library
-library work;
-use work.WF_PACKAGE.all;     -- definitions of types, constants, entities
+-- Component specific library
+library PROASIC3;            -- ProASIC3 library
+use PROASIC3.all;


 --=================================================================================================

--- a/nanofip.vhd
+++ b/nanofip.vhd
@@ -278,6 +278,7 @@ entity nanofip is

  ack_o      : out std_logic;                     -- WISHBONE acknowledge

+  TP39 : out std_logic;

  --  User Interface, JTAG Controller

@@ -300,8 +301,8 @@ architecture struc of nanofip is
 ---------------------------------------------------------------------------------------------------
 --                              Synplify Triple Module Redundancy                                --
 ---------------------------------------------------------------------------------------------------
- -- attribute syn_radhardlevel          : string;                                                --
- -- attribute syn_radhardlevel of struc : architecture is "tmr";                                 --
+  attribute syn_radhardlevel          : string;                                                --
+  attribute syn_radhardlevel of struc : architecture is "tmr";                                 --
 ---------------------------------------------------------------------------------------------------


@@ -333,7 +334,6 @@ architecture struc of nanofip is
  signal s_jc_mem_adr_rd                                           : std_logic_vector (8 downto 0);
  signal s_jc_tdo_byte                                             : std_logic_vector (7 downto 0);

-  signal s_jc_tdi_o, s_jc_tms_o, s_jc_tck_o, s_fd_txd_o,s_rston                : std_logic;


 --=================================================================================================
@@ -359,12 +359,10 @@ begin
  -------------------------------------------------------------
      nFIP_rst_o          => s_nfip_intern_rst,
      wb_rst_o            => s_wb_rst,
-      rston_o             => s_rston,
+      rston_o             => rston_o,
      fd_rstn_o           => fd_rstn_o);
  -------------------------------------------------------------

-      rston_o   <= s_rston;
-


 ---------------------------------------------------------------------------------------------------
@@ -479,12 +477,12 @@ begin
  -------------------------------------------------------------
    tx_byte_request_p_o        => s_tx_request_byte_p,
    tx_completed_p_o           => s_tx_completed_p,
-    tx_data_o                  => s_fd_txd_o,
+    tx_data_o                  => fd_txd_o,
    tx_enable_o                => fd_txena_o,
    tx_clk_o                   => fd_txck_o);
  -------------------------------------------------------------

-  fd_txd_o <= s_fd_txd_o;
+

 ---------------------------------------------------------------------------------------------------
 --                                      WF_jtag_controller                                       --
@@ -505,7 +503,7 @@ begin
    jc_mem_adr_rd_o => s_jc_mem_adr_rd);
  -----------------------------------------------------------------

-
+  TP39 <= s_jc_tdo_byte(0);

 ---------------------------------------------------------------------------------------------------
 --                                       WF_engine_control                                       --

--- a/wf_DualClkRAM_clka_rd_clkb_wr.vhd
+++ b/wf_DualClkRAM_clka_rd_clkb_wr.vhd
@@ -92,8 +92,8 @@ end WF_DualClkRAM_clka_rd_clkb_wr;
 --=================================================================================================
 architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is

--  type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
--  signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
+  type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
+  signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
  signal s_one, s_rwB     : std_logic;
  signal s_zeros          : std_logic_vector (7 downto 0);

@@ -114,7 +114,7 @@ begin
 -- The input DINB is written in the same position in the 3 memories.
 -- The output DOUTA from each memory is kept in the array s_data_o_A_array.

--  G_memory_triplication: for I in 0 to 2 generate
+  G_memory_triplication: for I in 0 to 2 generate

    UDualClkRam : DualClkRam
    port map (
@@ -130,18 +130,18 @@ begin

      RESETn => s_one,

-      DOUTA  => data_porta_o, --s_data_o_A_array(I),
+      DOUTA  => s_data_o_A_array(I),--data_porta_o, --s_data_o_A_array(I)
      DOUTB  => open);

--  end generate;
+  end generate;


 ---------------------------------------------------------------------------------------------------
 -- Combinatorial Majority_Voter

-- Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
--                                 (s_data_o_A_array(1) and s_data_o_A_array(2)) or
--                                 (s_data_o_A_array(2) and s_data_o_A_array(0));
+ Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
+                                 (s_data_o_A_array(1) and s_data_o_A_array(2)) or
+                                 (s_data_o_A_array(2) and s_data_o_A_array(0));

 end syn;
 --=================================================================================================

--- a/wf_jtag_controller.vhd
+++ b/wf_jtag_controller.vhd
--- a/wf_jtag_player.vhd
+++ b/wf_jtag_player.vhd
--- a/wf_package.vhd
+++ b/wf_package.vhd
@@ -137,13 +137,15 @@ package WF_package is
  constant c_MAX_FRAME_BITS : natural := 976; -- maximum number of TMS/ TDI bits that can be sent in
                                              -- one frame : 122 bytes * 8 bits

-  constant c_JC_TCK_DIV : unsigned (3 downto 0) := "1000"; -- JC_TCK is created by a frequency
+                                                           -- JC_TCK is created by a frequency
                                                           -- division of the 40 MHz uclk.
                                                           -- c_JC_TCK_div = 8 gives a JC_TCK of 5 MHz

  constant c_FOUR_JC_TCK_C_LGTH : integer       := 5;      -- length of a counter
                                                           -- counting 4 JC_TCK periods

+
+
 ---------------------------------------------------------------------------------------------------
 --                        Constant regarding the Model & Constructor decoding                    --
 ---------------------------------------------------------------------------------------------------
@@ -890,6 +892,7 @@ end component WF_rx_osc;
    dat_o        : out std_logic_vector (15 downto 0);
    jc_tms_o     : out std_logic;
    jc_tdi_o     : out std_logic;
+  TP39 : out std_logic;
    jc_tck_o     : out std_logic);
  -----------------------------------------------------------------
  end component nanofip;