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nanoFIP - Gateware
Commit 63cac757 authored by egousiou's avatar egousiou
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fd reset includes PoR 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@113 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent dfed9a67
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Showing with 366 additions and 271 deletions
nanofip.vhd
View file @ 63cac757
...@@ -319,8 +319,8 @@ architecture struc of nanofip is ...@@ -319,8 +319,8 @@ architecture struc of nanofip is
signal s_rst, s_rx_byte_ready, s_start_prod_p, s_rst_rx_osc, s_prod_request_byte_p : std_logic; signal s_rst, s_rx_byte_ready, s_start_prod_p, s_rst_rx_osc, s_prod_request_byte_p : std_logic;
signal s_prod_byte_ready_p, s_prod_last_byte_p, s_urst_r_edge, s_wb_we_synch : std_logic; signal s_prod_byte_ready_p, s_prod_last_byte_p, s_rstin_f_edge, s_wb_we_synch : std_logic;
signal s_urst_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch : std_logic; signal s_rstin_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch: std_logic;
signal s_fss_crc_fes_manch_ok_p, s_cons_fss_decoded_p, s_prod_ack, s_wb_ack_cons : std_logic; signal s_fss_crc_fes_manch_ok_p, s_cons_fss_decoded_p, s_prod_ack, s_wb_ack_cons : std_logic;
signal s_crc_wrong_p, s_reset_nFIP_and_FD_p, s_rx_manch_clk_p, s_rx_bit_clk_p : std_logic; signal s_crc_wrong_p, s_reset_nFIP_and_FD_p, s_rx_manch_clk_p, s_rx_bit_clk_p : std_logic;
signal s_var1_access_synch, s_var2_access_synch, s_var3_access_synch, s_wb_stb_synch : std_logic; signal s_var1_access_synch, s_var2_access_synch, s_var3_access_synch, s_wb_stb_synch : std_logic;
...@@ -353,7 +353,7 @@ begin ...@@ -353,7 +353,7 @@ begin
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
wb_clk_i => wclk_i, wb_clk_i => wclk_i,
nfip_urst_i => s_rst, nfip_rst_i => s_rst,
rstin_a_i => rstin_i, rstin_a_i => rstin_i,
wb_rst_a_i => rst_i, wb_rst_a_i => rst_i,
slone_a_i => slone_i, slone_a_i => slone_i,
...@@ -376,8 +376,8 @@ begin ...@@ -376,8 +376,8 @@ begin
c_id_a_i => c_id_i, c_id_a_i => c_id_i,
p3_lgth_a_i => p3_lgth_i, p3_lgth_a_i => p3_lgth_i,
--------------------------------------------------------- ---------------------------------------------------------
rsti_o => s_urst_synch, rstin_o => s_rstin_synch,
urst_r_edge_o => s_urst_r_edge, rstin_f_edge_o => s_rstin_f_edge,
slone_o => s_slone_synch, slone_o => s_slone_synch,
nostat_o => s_nostat_synch, nostat_o => s_nostat_synch,
fd_wdgn_o => s_fd_wdgn_synch, fd_wdgn_o => s_fd_wdgn_synch,
...@@ -412,8 +412,8 @@ begin ...@@ -412,8 +412,8 @@ begin
reset_unit : WF_reset_unit reset_unit : WF_reset_unit
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
rstin_i => s_urst_synch, rstin_i => s_rstin_synch,
urst_r_edge_i => s_urst_r_edge, rstin_f_edge_i => s_rstin_f_edge,
rstpon_i => rstpon_i, rstpon_i => rstpon_i,
rate_i => s_rate_synch, rate_i => s_rate_synch,
var_i => s_var_from_control, var_i => s_var_from_control,
...@@ -436,7 +436,7 @@ begin ...@@ -436,7 +436,7 @@ begin
c_TX_CLK_BUFF_LGTH => 4) c_TX_CLK_BUFF_LGTH => 4)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => s_rst, nfip_rst_i => s_rst,
rxd_edge_i => s_fd_rxd_edge_p, rxd_edge_i => s_fd_rxd_edge_p,
rst_rx_osc_i => s_rst_rx_osc, rst_rx_osc_i => s_rst_rx_osc,
rate_i => s_rate_synch, rate_i => s_rate_synch,
...@@ -459,7 +459,7 @@ begin ...@@ -459,7 +459,7 @@ begin
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
slone_i => slone_i, slone_i => slone_i,
nfip_urst_i => s_rst, nfip_rst_i => s_rst,
subs_i => s_subs_synch, subs_i => s_subs_synch,
fd_rxd_i => s_fd_rxd_synch, fd_rxd_i => s_fd_rxd_synch,
fd_rxd_r_edge_p_i => s_fd_rxd_r_edge_p, fd_rxd_r_edge_p_i => s_fd_rxd_r_edge_p,
...@@ -502,7 +502,7 @@ begin ...@@ -502,7 +502,7 @@ begin
uclk_i => uclk_i, uclk_i => uclk_i,
slone_i => slone_i, slone_i => slone_i,
nostat_i => nostat_i, nostat_i => nostat_i,
nfip_urst_i => s_rst, nfip_rst_i => s_rst,
wb_clk_i => wclk_i, wb_clk_i => wclk_i,
wb_data_i => s_wb_dati_synch, wb_data_i => s_wb_dati_synch,
wb_adr_i => s_wb_adri_synch, wb_adr_i => s_wb_adri_synch,
...@@ -552,7 +552,7 @@ begin ...@@ -552,7 +552,7 @@ begin
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => s_rst, nfip_rst_i => s_rst,
tx_request_byte_p_i => s_prod_request_byte_p, tx_request_byte_p_i => s_prod_request_byte_p,
rx_fss_received_p_i => s_cons_fss_decoded_p, rx_fss_received_p_i => s_cons_fss_decoded_p,
rx_byte_i => s_rx_byte, rx_byte_i => s_rx_byte,
...@@ -587,7 +587,7 @@ begin ...@@ -587,7 +587,7 @@ begin
model_constr_decoder : WF_model_constr_decoder model_constr_decoder : WF_model_constr_decoder
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => s_rst, nfip_rst_i => s_rst,
model_id_i => s_m_id_synch,-------------- model_id_i => s_m_id_synch,--------------
constr_id_i => s_c_id_synch, constr_id_i => s_c_id_synch,
--------------------------------------------------------- ---------------------------------------------------------
......
wf_bits_to_txd.vhd
View file @ 63cac757
...@@ -90,7 +90,7 @@ entity WF_bits_to_txd is ...@@ -90,7 +90,7 @@ entity WF_bits_to_txd is
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_tx_serializer unit -- Signals from the WF_tx_serializer unit
crc_byte_manch_i : in std_logic_vector (31 downto 0);--! manch. encoded CRC bytes to be sent crc_byte_manch_i : in std_logic_vector (31 downto 0);--! manch. encoded CRC bytes to be sent
...@@ -134,7 +134,7 @@ begin ...@@ -134,7 +134,7 @@ begin
Bits_Delivery: process (uclk_i) Bits_Delivery: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
txd_o <= '0'; txd_o <= '0';
else else
...@@ -171,7 +171,7 @@ begin ...@@ -171,7 +171,7 @@ begin
FD_TXENA_Generator: process (uclk_i) FD_TXENA_Generator: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
tx_enable_o <= '0'; tx_enable_o <= '0';
else else
......
wf_cons_bytes_processor.vhd
View file @ 63cac757
...@@ -117,7 +117,7 @@ port ( ...@@ -117,7 +117,7 @@ port (
slone_i : in std_logic; --! stand-alone mode (active high) slone_i : in std_logic; --! stand-alone mode (active high)
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk) -- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
wb_clk_i : in std_logic; --! WISHBONE clock wb_clk_i : in std_logic; --! WISHBONE clock
...@@ -226,7 +226,7 @@ begin ...@@ -226,7 +226,7 @@ begin
Consumed_Bytes_To_DATO: WF_cons_bytes_to_dato Consumed_Bytes_To_DATO: WF_cons_bytes_to_dato
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
transfer_byte_p_i => s_slone_write_byte_p, transfer_byte_p_i => s_slone_write_byte_p,
byte_i => byte_i, byte_i => byte_i,
------------------------------------------ ------------------------------------------
...@@ -438,7 +438,7 @@ Buffer_Ctrl_PDU_Length_bytes: process (uclk_i) ...@@ -438,7 +438,7 @@ Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
cons_ctrl_byte_o <= (others => '0'); cons_ctrl_byte_o <= (others => '0');
cons_pdu_byte_o <= (others => '0'); cons_pdu_byte_o <= (others => '0');
s_cons_lgth_byte <= (others => '0'); s_cons_lgth_byte <= (others => '0');
......
wf_cons_bytes_to_dato.vhd
View file @ 63cac757
...@@ -91,7 +91,7 @@ entity WF_cons_bytes_to_dato is ...@@ -91,7 +91,7 @@ entity WF_cons_bytes_to_dato is
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit -- Signal from the WF_reset_unit unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_cons_bytes_processor -- Signals from the WF_cons_bytes_processor
byte_i : in std_logic_vector (7 downto 0); --! de-serialised byte byte_i : in std_logic_vector (7 downto 0); --! de-serialised byte
...@@ -126,7 +126,7 @@ begin ...@@ -126,7 +126,7 @@ begin
Data_Transfer_To_Dat_o: process (uclk_i) Data_Transfer_To_Dat_o: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
slone_data_o <= (others => '0'); -- bus initialization slone_data_o <= (others => '0'); -- bus initialization
else else
......
wf_cons_outcome.vhd
View file @ 63cac757
...@@ -86,14 +86,14 @@ entity WF_cons_outcome is ...@@ -86,14 +86,14 @@ entity WF_cons_outcome is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk) -- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings (synchronized with uclk) -- nanoFIP WorldFIP Settings (synchronized with uclk)
subs_i : in std_logic_vector (7 downto 0); --! subscriber number coding subs_i : in std_logic_vector (7 downto 0); --! subscriber number coding
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_cons_frame_validator -- Signals from the WF_cons_frame_validator
cons_frame_ok_p_i : in std_logic; --! pulse after a correct cons frame cons_frame_ok_p_i : in std_logic; --! pulse after a correct cons frame
...@@ -173,7 +173,7 @@ begin ...@@ -173,7 +173,7 @@ begin
VAR_RDY_Generation: process (uclk_i) VAR_RDY_Generation: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
var1_rdy_o <= '0'; var1_rdy_o <= '0';
var2_rdy_o <= '0'; var2_rdy_o <= '0';
s_var1_received <= '0'; s_var1_received <= '0';
...@@ -235,7 +235,7 @@ begin ...@@ -235,7 +235,7 @@ begin
Cons_frame_ok_p_delay: process (uclk_i) Cons_frame_ok_p_delay: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
cons_frame_ok_p_d1 <= '0'; cons_frame_ok_p_d1 <= '0';
else else
cons_frame_ok_p_d1 <= cons_frame_ok_p_i; cons_frame_ok_p_d1 <= cons_frame_ok_p_i;
...@@ -254,7 +254,7 @@ begin ...@@ -254,7 +254,7 @@ begin
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_rst_nfip_and_fd <= '0'; s_rst_nfip_and_fd <= '0';
s_assert_rston <= '0'; s_assert_rston <= '0';
......
wf_consumption.vhd
View file @ 63cac757
...@@ -147,7 +147,7 @@ entity WF_consumption is ...@@ -147,7 +147,7 @@ entity WF_consumption is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit unit -- Signal from the WF_reset_unit unit
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
-- used by: all the units -- used by: all the units
...@@ -260,7 +260,7 @@ begin ...@@ -260,7 +260,7 @@ begin
generic map (c_DEGLITCH_LGTH => 10) generic map (c_DEGLITCH_LGTH => 10)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
rxd_i => fd_rxd_i, rxd_i => fd_rxd_i,
sample_bit_p_i => sample_bit_p_i, sample_bit_p_i => sample_bit_p_i,
sample_manch_bit_p_i => sample_manch_bit_p_i, sample_manch_bit_p_i => sample_manch_bit_p_i,
...@@ -281,7 +281,7 @@ begin ...@@ -281,7 +281,7 @@ begin
Consumption_Level_0_Deserializer: WF_rx_deserializer Consumption_Level_0_Deserializer: WF_rx_deserializer
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
rst_rx_unit_p_i => rst_rx_unit_p_i, rst_rx_unit_p_i => rst_rx_unit_p_i,
sample_bit_p_i => s_sample_bit_p, sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => signif_edge_window_i, signif_edge_window_i => signif_edge_window_i,
...@@ -311,7 +311,7 @@ begin ...@@ -311,7 +311,7 @@ begin
Consumption_Level_1_bytes_processor : WF_cons_bytes_processor Consumption_Level_1_bytes_processor : WF_cons_bytes_processor
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
slone_i => slone_i, slone_i => slone_i,
byte_ready_p_i => s_byte_ready_p, byte_ready_p_i => s_byte_ready_p,
var_i => var_i, var_i => var_i,
...@@ -366,7 +366,7 @@ begin ...@@ -366,7 +366,7 @@ begin
uclk_i => uclk_i, uclk_i => uclk_i,
slone_i => slone_i, slone_i => slone_i,
subs_i => subs_i, subs_i => subs_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
cons_frame_ok_p_i => s_cons_frame_ok_p, cons_frame_ok_p_i => s_cons_frame_ok_p,
var_i => var_i, var_i => var_i,
cons_var_rst_byte_1_i => s_cons_var_rst_byte_1, cons_var_rst_byte_1_i => s_cons_var_rst_byte_1,
......
wf_crc.vhd
View file @ 63cac757
...@@ -86,7 +86,7 @@ port ( ...@@ -86,7 +86,7 @@ port (
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_rx_deserializer/ WF_tx_serializer units -- Signals from the WF_rx_deserializer/ WF_tx_serializer units
data_bit_i : in std_logic; --! incoming data bit stream data_bit_i : in std_logic; --! incoming data bit stream
...@@ -146,7 +146,7 @@ CRC_calculation: process (uclk_i) ...@@ -146,7 +146,7 @@ CRC_calculation: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_q <= (others => '0'); s_q <= (others => '0');
else else
......
wf_decr_counter.vhd
View file @ 63cac757
...@@ -75,7 +75,7 @@ entity WF_decr_counter is ...@@ -75,7 +75,7 @@ entity WF_decr_counter is
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit -- Signals from any unit
counter_decr_p_i : in std_logic; --! decrement enable counter_decr_p_i : in std_logic; --! decrement enable
...@@ -110,7 +110,7 @@ begin ...@@ -110,7 +110,7 @@ begin
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_counter <= (others => '0'); s_counter <= (others => '0');
else else
......
wf_engine_control.vhd
View file @ 63cac757
...@@ -128,7 +128,7 @@ entity WF_engine_control is ...@@ -128,7 +128,7 @@ entity WF_engine_control is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...@@ -256,7 +256,7 @@ begin ...@@ -256,7 +256,7 @@ begin
Engine_Control_FSM_Sync: process (uclk_i) Engine_Control_FSM_Sync: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
control_st <= idle; control_st <= idle;
else else
control_st <= nx_control_st; control_st <= nx_control_st;
...@@ -582,7 +582,7 @@ begin ...@@ -582,7 +582,7 @@ begin
generic map(g_counter_lgth => 8) generic map(g_counter_lgth => 8)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
reinit_counter_i => s_rst_prod_bytes_counter, reinit_counter_i => s_rst_prod_bytes_counter,
incr_counter_i => s_inc_prod_bytes_counter, incr_counter_i => s_inc_prod_bytes_counter,
------------------------------------------------------- -------------------------------------------------------
...@@ -612,7 +612,7 @@ begin ...@@ -612,7 +612,7 @@ begin
generic map(g_counter_lgth => 8) generic map(g_counter_lgth => 8)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
reinit_counter_i => s_rst_rx_bytes_counter, reinit_counter_i => s_rst_rx_bytes_counter,
incr_counter_i => s_inc_rx_bytes_counter, incr_counter_i => s_inc_rx_bytes_counter,
------------------------------------------------------- -------------------------------------------------------
...@@ -689,7 +689,7 @@ begin ...@@ -689,7 +689,7 @@ begin
generic map(g_counter_lgth => 15) generic map(g_counter_lgth => 15)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
counter_top => s_time_counter_top, counter_top => s_time_counter_top,
counter_load_i => s_load_time_counter, counter_load_i => s_load_time_counter,
counter_decr_p_i => '1', -- on each uclk tick counter_decr_p_i => '1', -- on each uclk tick
...@@ -777,7 +777,7 @@ begin ...@@ -777,7 +777,7 @@ begin
ID_DAT_var: process (uclk_i) ID_DAT_var: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_var <= var_whatever; s_var <= var_whatever;
s_var_aux <= var_whatever; s_var_aux <= var_whatever;
else else
...@@ -838,7 +838,7 @@ begin ...@@ -838,7 +838,7 @@ begin
process (uclk_i) process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
tx_last_byte_p_o <= '0'; tx_last_byte_p_o <= '0';
s_tx_last_byte_p_d <= '0'; s_tx_last_byte_p_d <= '0';
s_tx_byte_ready_p_d1 <= '0'; s_tx_byte_ready_p_d1 <= '0';
......
wf_incr_counter.vhd
View file @ 63cac757
...@@ -69,7 +69,7 @@ entity WF_incr_counter is ...@@ -69,7 +69,7 @@ entity WF_incr_counter is
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit -- Signals from any unit
incr_counter_i : in std_logic; --! increment enable incr_counter_i : in std_logic; --! increment enable
...@@ -107,7 +107,7 @@ begin ...@@ -107,7 +107,7 @@ begin
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_counter <= (others => '0'); s_counter <= (others => '0');
elsif reinit_counter_i = '1' then elsif reinit_counter_i = '1' then
......
wf_inputs_synchronizer.vhd
View file @ 63cac757
...@@ -90,7 +90,7 @@ entity WF_inputs_synchronizer is ...@@ -90,7 +90,7 @@ entity WF_inputs_synchronizer is
slone_a_i : in std_logic; slone_a_i : in std_logic;
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP WorldFIP Settings -- nanoFIP WorldFIP Settings
c_id_a_i : in std_logic_vector(3 downto 0); c_id_a_i : in std_logic_vector(3 downto 0);
...@@ -123,9 +123,9 @@ entity WF_inputs_synchronizer is ...@@ -123,9 +123,9 @@ entity WF_inputs_synchronizer is
-- OUTPUTS -- OUTPUTS
-- nanoFIP User Interface, General signals -- nanoFIP User Interface, General signals
nostat_o : out std_logic; nostat_o : out std_logic;
rsti_o : out std_logic; rstin_o : out std_logic;
slone_o : out std_logic; slone_o : out std_logic;
urst_r_edge_o : out std_logic; rstin_f_edge_o : out std_logic;
-- nanoFIP WorldFIP Settings -- nanoFIP WorldFIP Settings
c_id_o : out std_logic_vector(3 downto 0); c_id_o : out std_logic_vector(3 downto 0);
...@@ -192,12 +192,12 @@ begin ...@@ -192,12 +192,12 @@ begin
RSTIN_synchronisation_with_uclk: process (uclk_i) RSTIN_synchronisation_with_uclk: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (2 downto 0) & (not rstin_a_i); s_u_rst_d3 <= s_u_rst_d3 (2 downto 0) & rstin_a_i;
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rsti_o <= s_u_rst_d3(2); -- active high rstin_o <= s_u_rst_d3(2);
urst_r_edge_o <= not s_u_rst_d3(3) and s_u_rst_d3(2); rstin_f_edge_o <= s_u_rst_d3(3) and (not s_u_rst_d3(2));
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -205,7 +205,7 @@ begin ...@@ -205,7 +205,7 @@ begin
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_slone_d3 <= (others => '0'); s_slone_d3 <= (others => '0');
s_nostat_d3 <= (others => '0'); s_nostat_d3 <= (others => '0');
else else
...@@ -224,7 +224,7 @@ begin ...@@ -224,7 +224,7 @@ begin
FIELDRIVE_inputs_synchronisation: process (uclk_i) FIELDRIVE_inputs_synchronisation: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_fd_rxd_d3 <= (others => '0'); s_fd_rxd_d3 <= (others => '0');
s_fd_wdgn_d3 <= (others => '0'); s_fd_wdgn_d3 <= (others => '0');
s_fd_txer_d3 <= (others => '0'); s_fd_txer_d3 <= (others => '0');
...@@ -255,7 +255,7 @@ begin ...@@ -255,7 +255,7 @@ begin
VAR_ACC_synchronisation: process (uclk_i) VAR_ACC_synchronisation: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_var1_access_d1 <= '0'; s_var1_access_d1 <= '0';
s_var1_access_d2 <= '0'; s_var1_access_d2 <= '0';
s_var1_access_d3 <= '0'; s_var1_access_d3 <= '0';
...@@ -347,7 +347,7 @@ begin ...@@ -347,7 +347,7 @@ begin
Slone_dat_i_synchronization: process (uclk_i) Slone_dat_i_synchronization: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_slone_dati_d1 <= (others => '0'); s_slone_dati_d1 <= (others => '0');
s_slone_dati_d2 <= (others => '0'); s_slone_dati_d2 <= (others => '0');
s_slone_dati_d3 <= (others => '0'); s_slone_dati_d3 <= (others => '0');
...@@ -368,7 +368,7 @@ begin ...@@ -368,7 +368,7 @@ begin
WorldFIP_Settings_synchronisation: process (uclk_i) WorldFIP_Settings_synchronisation: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_rate_d1 <= (others => '0'); s_rate_d1 <= (others => '0');
s_rate_d2 <= (others => '0'); s_rate_d2 <= (others => '0');
s_rate_d3 <= (others => '0'); s_rate_d3 <= (others => '0');
......
wf_manch_code_viol_check.vhd
View file @ 63cac757
...@@ -93,7 +93,7 @@ entity WF_rx_manch_code_check is ...@@ -93,7 +93,7 @@ entity WF_rx_manch_code_check is
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_rx_deglitcher unit -- Signals from the WF_rx_deglitcher unit
sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
...@@ -135,7 +135,7 @@ begin ...@@ -135,7 +135,7 @@ begin
Check_code_violations: process (uclk_i) Check_code_violations: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_check_code_viol_p <= '0'; s_check_code_viol_p <= '0';
s_sample_bit_p_d1 <= '0'; s_sample_bit_p_d1 <= '0';
s_sample_bit_p_d2 <= '0'; s_sample_bit_p_d2 <= '0';
......
wf_model_constr_decoder.vhd
View file @ 63cac757
...@@ -94,7 +94,7 @@ entity WF_model_constr_decoder is ...@@ -94,7 +94,7 @@ entity WF_model_constr_decoder is
uclk_i : in std_logic; --! 40 Mhz clock uclk_i : in std_logic; --! 40 Mhz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP WorldFIP Settings (synchronised with uclk_i) -- nanoFIP WorldFIP Settings (synchronised with uclk_i)
constr_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings constr_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
...@@ -144,7 +144,7 @@ begin ...@@ -144,7 +144,7 @@ begin
Model_Constructor_Decoder: process (uclk_i) Model_Constructor_Decoder: process (uclk_i)
begin begin
if rising_edge (uclk_i) then -- initializations if rising_edge (uclk_i) then -- initializations
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
model_id_dec_o <= (others => '0'); model_id_dec_o <= (others => '0');
constr_id_dec_o <= (others => '0'); constr_id_dec_o <= (others => '0');
s_model_stage1 <= (others => '0'); s_model_stage1 <= (others => '0');
...@@ -185,7 +185,7 @@ begin ...@@ -185,7 +185,7 @@ begin
generic map(g_counter_lgth => 2) generic map(g_counter_lgth => 2)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
reinit_counter_i => '0', reinit_counter_i => '0',
incr_counter_i => '1', incr_counter_i => '1',
----------------------------------------- -----------------------------------------
......
wf_package.vhd
View file @ 63cac757
...@@ -350,7 +350,7 @@ package WF_package is ...@@ -350,7 +350,7 @@ package WF_package is
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
wb_clk_i : in std_logic; wb_clk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
rstin_a_i : in std_logic; rstin_a_i : in std_logic;
wb_rst_a_i : in std_logic; wb_rst_a_i : in std_logic;
slone_a_i : in std_logic; slone_a_i : in std_logic;
...@@ -373,8 +373,8 @@ package WF_package is ...@@ -373,8 +373,8 @@ package WF_package is
c_id_a_i : in std_logic_vector(3 downto 0); c_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0); p3_lgth_a_i : in std_logic_vector(2 downto 0);
----------------------------------------------------------------- -----------------------------------------------------------------
rsti_o : out std_logic; rstin_o : out std_logic;
urst_r_edge_o : out std_logic; rstin_f_edge_o : out std_logic;
slone_o : out std_logic; slone_o : out std_logic;
nostat_o : out std_logic; nostat_o : out std_logic;
fd_wdgn_o : out std_logic; fd_wdgn_o : out std_logic;
...@@ -407,7 +407,7 @@ end component WF_inputs_synchronizer; ...@@ -407,7 +407,7 @@ end component WF_inputs_synchronizer;
component WF_rx_deserializer component WF_rx_deserializer
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
rst_rx_unit_p_i : in std_logic; rst_rx_unit_p_i : in std_logic;
signif_edge_window_i : in std_logic; signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic; adjac_bits_window_i : in std_logic;
...@@ -434,7 +434,7 @@ end component WF_inputs_synchronizer; ...@@ -434,7 +434,7 @@ end component WF_inputs_synchronizer;
generic (c_TX_CLK_BUFF_LGTH : natural); generic (c_TX_CLK_BUFF_LGTH : natural);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
start_prod_p_i : in std_logic; start_prod_p_i : in std_logic;
byte_ready_p_i : in std_logic; byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic; last_byte_p_i : in std_logic;
...@@ -456,7 +456,7 @@ end component WF_inputs_synchronizer; ...@@ -456,7 +456,7 @@ end component WF_inputs_synchronizer;
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0); rate_i : in std_logic_vector (1 downto 0);
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
rxd_edge_i : in std_logic; rxd_edge_i : in std_logic;
rst_rx_osc_i : in std_logic; rst_rx_osc_i : in std_logic;
------------------------------------------------------------------------- -------------------------------------------------------------------------
...@@ -476,7 +476,7 @@ end component WF_inputs_synchronizer; ...@@ -476,7 +476,7 @@ end component WF_inputs_synchronizer;
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
slone_i : in std_logic; slone_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
wb_clk_i : in std_logic; wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0); wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic; wb_stb_r_edge_p_i : in std_logic;
...@@ -502,7 +502,7 @@ end component WF_inputs_synchronizer; ...@@ -502,7 +502,7 @@ end component WF_inputs_synchronizer;
component WF_cons_bytes_to_dato is component WF_cons_bytes_to_dato is
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
transfer_byte_p_i : in std_logic_vector (1 downto 0); transfer_byte_p_i : in std_logic_vector (1 downto 0);
byte_i : in std_logic_vector (7 downto 0); byte_i : in std_logic_vector (7 downto 0);
--------------------------------------------------------------- ---------------------------------------------------------------
...@@ -519,7 +519,7 @@ end component WF_inputs_synchronizer; ...@@ -519,7 +519,7 @@ end component WF_inputs_synchronizer;
uclk_i : in std_logic; uclk_i : in std_logic;
slone_i : in std_logic; slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); subs_i : in std_logic_vector (7 downto 0);
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
fd_rxd_i : in std_logic; fd_rxd_i : in std_logic;
fd_rxd_r_edge_p_i : in std_logic; fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic; fd_rxd_f_edge_p_i : in std_logic;
...@@ -559,7 +559,7 @@ end component WF_inputs_synchronizer; ...@@ -559,7 +559,7 @@ end component WF_inputs_synchronizer;
uclk_i : in std_logic; uclk_i : in std_logic;
slone_i : in std_logic; slone_i : in std_logic;
nostat_i : in std_logic; nostat_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
wb_clk_i : in std_logic; wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector(7 downto 0); wb_data_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(9 downto 0); wb_adr_i : in std_logic_vector(9 downto 0);
...@@ -606,7 +606,7 @@ end component WF_production; ...@@ -606,7 +606,7 @@ end component WF_production;
uclk_i : in std_logic; uclk_i : in std_logic;
slone_i : in std_logic; slone_i : in std_logic;
nostat_i : in std_logic; nostat_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
model_id_dec_i : in std_logic_vector (7 downto 0); model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0); constr_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic; wb_clk_i : in std_logic;
...@@ -636,7 +636,7 @@ end component WF_production; ...@@ -636,7 +636,7 @@ end component WF_production;
component WF_prod_bytes_from_dati is component WF_prod_bytes_from_dati is
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0); slone_data_i : in std_logic_vector (15 downto 0);
var3_rdy_i : in std_logic; var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0); byte_index_i : in std_logic_vector (7 downto 0);
...@@ -652,7 +652,7 @@ end component WF_production; ...@@ -652,7 +652,7 @@ end component WF_production;
generic ( c_QUARTZ_PERIOD : real); generic ( c_QUARTZ_PERIOD : real);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0); rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0); subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0); p3_lgth_i : in std_logic_vector (2 downto 0);
...@@ -682,8 +682,8 @@ end component WF_production; ...@@ -682,8 +682,8 @@ end component WF_production;
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
rstin_i : in std_logic; rstin_i : in std_logic;
urst_r_edge_i : in std_logic; rstin_f_edge_i : in std_logic;
rstpon_i : in std_logic; rstpon_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0); rate_i : in std_logic_vector (1 downto 0);
var_i : in t_var; var_i : in t_var;
rst_nFIP_and_FD_p_i : in std_logic; rst_nFIP_and_FD_p_i : in std_logic;
...@@ -720,7 +720,7 @@ end component WF_production; ...@@ -720,7 +720,7 @@ end component WF_production;
generic (c_GENERATOR_POLY_length : natural := 16); generic (c_GENERATOR_POLY_length : natural := 16);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
start_crc_p_i : in std_logic; start_crc_p_i : in std_logic;
data_bit_i : in std_logic; data_bit_i : in std_logic;
data_bit_ready_p_i : in std_logic; data_bit_ready_p_i : in std_logic;
...@@ -748,7 +748,7 @@ end component WF_production; ...@@ -748,7 +748,7 @@ end component WF_production;
component WF_rx_manch_code_check is component WF_rx_manch_code_check is
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
serial_input_signal_i : in std_logic; serial_input_signal_i : in std_logic;
sample_bit_p_i : in std_logic; sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic; sample_manch_bit_p_i : in std_logic;
...@@ -764,7 +764,7 @@ end component WF_production; ...@@ -764,7 +764,7 @@ end component WF_production;
generic (c_DEGLITCH_LGTH : integer := 10); generic (c_DEGLITCH_LGTH : integer := 10);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
rxd_i : in std_logic; rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic; sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic; sample_bit_p_i : in std_logic;
...@@ -783,7 +783,7 @@ end component WF_production; ...@@ -783,7 +783,7 @@ end component WF_production;
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
slone_i : in std_logic; slone_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
fd_wdgn_i : in std_logic; fd_wdgn_i : in std_logic;
fd_txer_i : in std_logic; fd_txer_i : in std_logic;
var1_acc_i : in std_logic; var1_acc_i : in std_logic;
...@@ -812,7 +812,7 @@ end component WF_production; ...@@ -812,7 +812,7 @@ end component WF_production;
generic (c_TX_CLK_BUFF_LGTH : natural := 4); generic (c_TX_CLK_BUFF_LGTH : natural := 4);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
txd_bit_index_i : in unsigned(4 downto 0); txd_bit_index_i : in unsigned(4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0); data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0); crc_byte_manch_i : in std_logic_vector (31 downto 0);
...@@ -846,6 +846,7 @@ end component WF_production; ...@@ -846,6 +846,7 @@ end component WF_production;
slone_i : in std_logic; slone_i : in std_logic;
nostat_i : in std_logic; nostat_i : in std_logic;
rstin_i : in std_logic; rstin_i : in std_logic;
rstpon_i : in std_logic;
var1_acc_i : in std_logic; var1_acc_i : in std_logic;
var2_acc_i : in std_logic; var2_acc_i : in std_logic;
var3_acc_i : in std_logic; var3_acc_i : in std_logic;
...@@ -881,7 +882,7 @@ end component WF_production; ...@@ -881,7 +882,7 @@ end component WF_production;
component WF_model_constr_decoder component WF_model_constr_decoder
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
model_id_i : in std_logic_vector (3 downto 0); model_id_i : in std_logic_vector (3 downto 0);
constr_id_i : in std_logic_vector (3 downto 0); constr_id_i : in std_logic_vector (3 downto 0);
--------------------------------------------------------------- ---------------------------------------------------------------
...@@ -898,7 +899,7 @@ end component WF_production; ...@@ -898,7 +899,7 @@ end component WF_production;
generic (g_counter_lgth : natural := 5); generic (g_counter_lgth : natural := 5);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
counter_top : in unsigned (g_counter_lgth-1 downto 0); counter_top : in unsigned (g_counter_lgth-1 downto 0);
counter_load_i : in std_logic; counter_load_i : in std_logic;
counter_decr_p_i : in std_logic; counter_decr_p_i : in std_logic;
...@@ -915,7 +916,7 @@ end component WF_production; ...@@ -915,7 +916,7 @@ end component WF_production;
generic (g_counter_lgth : natural := 8); generic (g_counter_lgth : natural := 8);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
reinit_counter_i : in std_logic; reinit_counter_i : in std_logic;
incr_counter_i : in std_logic; incr_counter_i : in std_logic;
--------------------------------------------------------------- ---------------------------------------------------------------
...@@ -963,7 +964,7 @@ end component WF_production; ...@@ -963,7 +964,7 @@ end component WF_production;
uclk_i : in std_logic; uclk_i : in std_logic;
slone_i : in std_logic; slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); subs_i : in std_logic_vector (7 downto 0);
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
cons_frame_ok_p_i : in std_logic; cons_frame_ok_p_i : in std_logic;
var_i : in t_var; var_i : in t_var;
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0); cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
...@@ -982,7 +983,7 @@ component WF_prod_permit is ...@@ -982,7 +983,7 @@ component WF_prod_permit is
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
var_i : in t_var; var_i : in t_var;
var3_rdy_o : out std_logic var3_rdy_o : out std_logic
); );
......
wf_prod_bytes_retriever.vhd
View file @ 63cac757
This diff is collapsed.
wf_prod_bytes_to_dati.vhd
View file @ 63cac757
...@@ -58,7 +58,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -58,7 +58,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 11/2010 v0.01 EG unit created --! -> 11/2010 v0.01 EG unit created
--! -> 4/1/2011 v0.02 EG unit renamed from WF_slone_prod_dati_bytes_sampler to --! -> 4/1/2011 v0.02 EG unit renamed from WF_slone_prod_dati_bytes_sampler to
--! WF_prod_bytes_from_dati; cleaning-up + commenting --! WF_prod_bytes_from_dati; cleaning-up + commenting
--!
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -85,21 +84,21 @@ entity WF_prod_bytes_from_dati is ...@@ -85,21 +84,21 @@ entity WF_prod_bytes_from_dati is
-- nanoFIP User Interface, General signals -- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, NON-WISHBONE -- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- (synchronised with uclk) -- (synchronised with uclk)
-- Signals from the WF_engine_control -- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- Signals from the WF_prod_permit -- Signals from the WF_prod_permit unit
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- OUTPUTS -- OUTPUTS
-- Signal to the WF_prod_bytes_retriever -- Signal to the WF_prod_bytes_retriever
slone_byte_o : out std_logic_vector (7 downto 0) --! byte to be sent slone_byte_o : out std_logic_vector (7 downto 0) --! sampled byte to be sent
); );
end entity WF_prod_bytes_from_dati; end entity WF_prod_bytes_from_dati;
...@@ -127,7 +126,7 @@ begin ...@@ -127,7 +126,7 @@ begin
Sample_DAT_I_bus: process (uclk_i) Sample_DAT_I_bus: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_var3_rdy_d4 <= (others=>'0'); s_var3_rdy_d4 <= (others=>'0');
s_sampled_data <= (others=>'0'); s_sampled_data <= (others=>'0');
......
wf_prod_permit.vhd
View file @ 63cac757
...@@ -83,7 +83,7 @@ entity WF_prod_permit is ...@@ -83,7 +83,7 @@ entity WF_prod_permit is
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control -- Signals from the WF_engine_control
var_i : in t_var; --! variable type that is being treated var_i : in t_var; --! variable type that is being treated
...@@ -125,7 +125,7 @@ begin ...@@ -125,7 +125,7 @@ begin
VAR_RDY_Generation: process (uclk_i) VAR_RDY_Generation: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
var3_rdy_o <= '0'; var3_rdy_o <= '0';
else else
......
wf_production.vhd
View file @ 63cac757
...@@ -27,7 +27,42 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -27,7 +27,42 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- --
--! @brief --! @brief The unit gathers the main actions that regard data production.
--! It instantiates the units:
--!
--! o WF_tx_serializerr : that receives bytes from the WF_prod_bytes_retriever,
--! encodes them (Manchester 2), adds the FSS, FCS & FES
--! fields and puts one by one the encoded bits to the
--! FIELDRIVE output FD_TXD.
--! o WF_prod_bytes_retriever : that retreives user-data bytes from the Produced RAM
--! or the "nanoFIP User Interface, NON-WISHBONE" data bus
--! DAT_I, and other bytes(PDU,LGTH,Ctrl,MPS,nFIP status)
--! from the WF_package, WF_status_bytes_gen,
--! WF_prod_data_lgth_calc units.
--! o WF_status_bytes_gen : that receives information from the WF_consumption
--!
--! o WF_prod_permit : that handles the"nanoFIP User Interface, NON-WISHBONE"
--! signal VAR3_RDY
--!
--! __ _________________________________
--! | | |
--! Level 2 | WF_prod_permit |
--! |__ |_________________________________|
--! ^
--! __ _________________________________ ________________
--! | | | | |
--! Level 1 | WF_prod_bytes_retriever | < | WF_status_bytes|
--! | | | | _gen |
--! |__ |_________________________________| |________________|
--! ^
--! __ _________________________________
--! | | |
--! Level 0 | WF_tx_serializerr |
--! |__ |_________________________________|
--!
--! _______________________________________________________________
--! 0__________________________FIELDBUS____________________________O
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
...@@ -92,7 +127,7 @@ entity WF_production is ...@@ -92,7 +127,7 @@ entity WF_production is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit unit -- Signal from the WF_reset_unit unit
nfip_urst_i : in std_logic; nfip_rst_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk) -- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
...@@ -199,28 +234,25 @@ architecture struc of WF_production is ...@@ -199,28 +234,25 @@ architecture struc of WF_production is
--================================================================================================= --=================================================================================================
begin begin
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_tx_serializer unit
production_level_0: WF_tx_serializer ---------------------------------------------------------------------------------------------------
generic map(c_TX_CLK_BUFF_LGTH => c_TX_CLK_BUFF_LGTH) -- Production Level 3 : VAR3_RDY generator --
PORT MAP( ---------------------------------------------------------------------------------------------------
uclk_i => uclk_i, VAR3_RDY_generation: WF_prod_permit
nfip_urst_i => nfip_urst_i, port map(
start_prod_p_i => start_prod_p_i, uclk_i => uclk_i,
byte_ready_p_i => byte_ready_p_i, nfip_rst_i => nfip_rst_i,
byte_i => s_byte_to_tx, var_i => var_i,
last_byte_p_i => last_byte_p_i,
tx_clk_p_buff_i => tx_clk_p_buff_i,
----------------------------------------------- -----------------------------------------------
tx_data_o => tx_data_o, var3_rdy_o => s_var3_rdy
request_byte_p_o => request_byte_p_o,
tx_enable_o => tx_enable_o
----------------------------------------------- -----------------------------------------------
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Production Level 1 : Bytes Retreival --
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_prod_bytes_retriever unit --!@brief Instantiation of the WF_prod_bytes_retriever unit
production_level_1 : WF_prod_bytes_retriever production_level_1 : WF_prod_bytes_retriever
...@@ -230,7 +262,7 @@ begin ...@@ -230,7 +262,7 @@ begin
constr_id_dec_i => constr_id_dec_i, constr_id_dec_i => constr_id_dec_i,
slone_i => slone_i, slone_i => slone_i,
nostat_i => nostat_i, nostat_i => nostat_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
wb_clk_i => wb_clk_i, wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i, wb_adr_i => wb_adr_i,
wb_stb_r_edge_p_i => wb_stb_r_edge_p_i, wb_stb_r_edge_p_i => wb_stb_r_edge_p_i,
...@@ -252,13 +284,17 @@ begin ...@@ -252,13 +284,17 @@ begin
----------------------------------------------- -----------------------------------------------
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Production Level 1 : Status Byte generation --
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_status_bytes_gen unit --!@brief Instantiation of the WF_status_bytes_gen unit
status_bytes_gen : WF_status_bytes_gen status_bytes_gen : WF_status_bytes_gen
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
slone_i => slone_i, slone_i => slone_i,
fd_wdgn_i => fd_wdgn_i, fd_wdgn_i => fd_wdgn_i,
fd_txer_i => fd_txer_i, fd_txer_i => fd_txer_i,
...@@ -281,14 +317,27 @@ begin ...@@ -281,14 +317,27 @@ begin
----------------------------------------------- -----------------------------------------------
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
VAR3_RDY_generation: WF_prod_permit -- Production Level 0 : Serializer --
port map( ---------------------------------------------------------------------------------------------------
uclk_i => uclk_i, --!@brief Instantiation of the WF_tx_serializer unit
nfip_urst_i => nfip_urst_i,
var_i => var_i, production_level_0: WF_tx_serializer
generic map(c_TX_CLK_BUFF_LGTH => c_TX_CLK_BUFF_LGTH)
PORT MAP(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_prod_p_i => start_prod_p_i,
byte_ready_p_i => byte_ready_p_i,
byte_i => s_byte_to_tx,
last_byte_p_i => last_byte_p_i,
tx_clk_p_buff_i => tx_clk_p_buff_i,
----------------------------------------------- -----------------------------------------------
var3_rdy_o => s_var3_rdy tx_data_o => tx_data_o,
request_byte_p_o => request_byte_p_o,
tx_enable_o => tx_enable_o
----------------------------------------------- -----------------------------------------------
); );
......
wf_reset_unit.vhd
View file @ 63cac757
This diff is collapsed.
wf_rx_deglitcher.vhd
View file @ 63cac757
...@@ -94,7 +94,7 @@ entity WF_rx_deglitcher is ...@@ -94,7 +94,7 @@ entity WF_rx_deglitcher is
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk) -- nanoFIP FIELDRIVE (synchronized with uclk)
rxd_i : in std_logic; --! ____|--------|________|--------|________ rxd_i : in std_logic; --! ____|--------|________|--------|________
...@@ -140,7 +140,7 @@ begin ...@@ -140,7 +140,7 @@ begin
Zeros_and_Ones_counter: process (uclk_i) Zeros_and_Ones_counter: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_zeros_and_ones_c <= (others =>'0'); s_zeros_and_ones_c <= (others =>'0');
else else
...@@ -167,7 +167,7 @@ end process; ...@@ -167,7 +167,7 @@ end process;
Filtering: process (uclk_i) Filtering: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_rxd_filtered <= '0'; s_rxd_filtered <= '0';
s_rxd_filtered_d <= '0'; s_rxd_filtered_d <= '0';
else else
...@@ -191,7 +191,7 @@ end process; ...@@ -191,7 +191,7 @@ end process;
Detect_f_edge_rxd_filtered: process (uclk_i) Detect_f_edge_rxd_filtered: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_rxd_filtered_buff <= (others => '0'); s_rxd_filtered_buff <= (others => '0');
else else
......
wf_rx_deserializer.vhd
View file @ 63cac757
...@@ -131,7 +131,7 @@ entity WF_rx_deserializer is ...@@ -131,7 +131,7 @@ entity WF_rx_deserializer is
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_engine_control unit -- Signal from the WF_engine_control unit
rst_rx_unit_p_i : in std_logic; --! reset of the unit rst_rx_unit_p_i : in std_logic; --! reset of the unit
...@@ -225,7 +225,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -225,7 +225,7 @@ architecture rtl of WF_rx_deserializer is
Deserializer_FSM_Sync: process (uclk_i) Deserializer_FSM_Sync: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
rx_st <= idle; rx_st <= idle;
else else
rx_st <= nx_rx_st; rx_st <= nx_rx_st;
...@@ -444,7 +444,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -444,7 +444,7 @@ architecture rtl of WF_rx_deserializer is
Append_Bit_To_Byte: process (uclk_i) Append_Bit_To_Byte: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
byte_ready_p_o <='0'; byte_ready_p_o <='0';
s_byte <= (others => '0'); s_byte <= (others => '0');
else else
...@@ -476,7 +476,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -476,7 +476,7 @@ architecture rtl of WF_rx_deserializer is
generic map(g_counter_lgth => 4) generic map(g_counter_lgth => 4)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
counter_top => s_manch_bit_index_top, counter_top => s_manch_bit_index_top,
counter_load_i => s_manch_bit_index_load, counter_load_i => s_manch_bit_index_load,
counter_decr_p_i => s_decr_manch_bit_index_p, counter_decr_p_i => s_decr_manch_bit_index_p,
...@@ -546,7 +546,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -546,7 +546,7 @@ architecture rtl of WF_rx_deserializer is
FES_Detector: process (uclk_i) FES_Detector: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_fes_detection_window <= '1'; s_fes_detection_window <= '1';
else else
...@@ -573,7 +573,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -573,7 +573,7 @@ architecture rtl of WF_rx_deserializer is
generic map(c_GENERATOR_POLY_length => 16) generic map(c_GENERATOR_POLY_length => 16)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_receiving_fsd, start_crc_p_i => s_receiving_fsd,
data_bit_ready_p_i => s_write_bit_to_byte, data_bit_ready_p_i => s_write_bit_to_byte,
data_bit_i => rxd_filtered_i, data_bit_i => rxd_filtered_i,
...@@ -588,7 +588,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -588,7 +588,7 @@ architecture rtl of WF_rx_deserializer is
Manch_Encoding_Verification: WF_rx_manch_code_check Manch_Encoding_Verification: WF_rx_manch_code_check
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
serial_input_signal_i => rxd_filtered_i, serial_input_signal_i => rxd_filtered_i,
sample_bit_p_i => sample_bit_p_i, sample_bit_p_i => sample_bit_p_i,
sample_manch_bit_p_i => sample_manch_bit_p_i, sample_manch_bit_p_i => sample_manch_bit_p_i,
...@@ -604,7 +604,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -604,7 +604,7 @@ architecture rtl of WF_rx_deserializer is
Code_viol: process (uclk_i) Code_viol: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_manch_not_ok <= '0'; s_manch_not_ok <= '0';
else else
...@@ -633,7 +633,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -633,7 +633,7 @@ architecture rtl of WF_rx_deserializer is
CRC_OK_pulse_delay: process (uclk_i) CRC_OK_pulse_delay: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_CRC_ok_p_buff <= (others => '0'); s_CRC_ok_p_buff <= (others => '0');
s_sample_manch_bit_p_d1 <= '0'; s_sample_manch_bit_p_d1 <= '0';
......
wf_rx_tx_osc.vhd
View file @ 63cac757
...@@ -116,7 +116,7 @@ entity WF_rx_tx_osc is ...@@ -116,7 +116,7 @@ entity WF_rx_tx_osc is
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_synchronizer unit -- Signal from the WF_synchronizer unit
rxd_edge_i : in std_logic; --! indication of an edge on fd_rxd rxd_edge_i : in std_logic; --! indication of an edge on fd_rxd
...@@ -207,7 +207,7 @@ begin ...@@ -207,7 +207,7 @@ begin
rx_periods_count: process (uclk_i) rx_periods_count: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_rx_counter <= (others => '0'); s_rx_counter <= (others => '0');
else else
...@@ -282,7 +282,7 @@ begin ...@@ -282,7 +282,7 @@ begin
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
-- initializations: -- initializations:
if (nfip_urst_i = '1') then if (nfip_rst_i = '1') then
s_rx_manch_clk <='0'; s_rx_manch_clk <='0';
s_rx_bit_clk <='0'; s_rx_bit_clk <='0';
s_rx_bit_clk_d1 <='0'; s_rx_bit_clk_d1 <='0';
...@@ -359,7 +359,7 @@ begin ...@@ -359,7 +359,7 @@ begin
tx_periods_count: process (uclk_i) tx_periods_count: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_tx_counter <= (others => '0'); s_tx_counter <= (others => '0');
s_tx_clk_p_buff <= (others => '0'); s_tx_clk_p_buff <= (others => '0');
s_tx_clk_d1 <= '0'; s_tx_clk_d1 <= '0';
......
wf_status_bytes_gen.vhd
View file @ 63cac757
...@@ -108,7 +108,7 @@ port ( ...@@ -108,7 +108,7 @@ port (
slone_i : in std_logic; --! stand-alone mode slone_i : in std_logic; --! stand-alone mode
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanaoFIP internal reset nfip_rst_i : in std_logic; --! nanaoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk) -- nanoFIP FIELDRIVE (synchronized with uclk)
fd_txer_i : in std_logic; --! transmitter error fd_txer_i : in std_logic; --! transmitter error
...@@ -173,7 +173,7 @@ begin ...@@ -173,7 +173,7 @@ begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if (nfip_urst_i = '1') then if (nfip_rst_i = '1') then
s_nFIP_status_byte <= (others => '0'); s_nFIP_status_byte <= (others => '0');
else else
...@@ -250,7 +250,7 @@ begin ...@@ -250,7 +250,7 @@ begin
-- generic map (g_counter_lgth => 4) -- generic map (g_counter_lgth => 4)
-- port map( -- port map(
-- uclk_i => uclk_i, -- uclk_i => uclk_i,
-- nfip_urst_i => nfip_urst_i, -- nfip_rst_i => nfip_rst_i,
-- reinit_counter_i => var1_rdy_i, -- reinit_counter_i => var1_rdy_i,
-- incr_counter_i => s_var1_rdy_incr_c, -- incr_counter_i => s_var1_rdy_incr_c,
-- counter_o => s_var1_rdy_c, -- counter_o => s_var1_rdy_c,
...@@ -266,7 +266,7 @@ begin ...@@ -266,7 +266,7 @@ begin
-- generic map (g_counter_lgth => 4) -- generic map (g_counter_lgth => 4)
-- port map( -- port map(
-- uclk_i => uclk_i, -- uclk_i => uclk_i,
-- nfip_urst_i => nfip_urst_i, -- nfip_rst_i => nfip_rst_i,
-- reinit_counter_i => var2_rdy_i, -- reinit_counter_i => var2_rdy_i,
-- incr_counter_i => s_var2_rdy_incr_c, -- incr_counter_i => s_var2_rdy_incr_c,
-- counter_o => s_var2_rdy_c, -- counter_o => s_var2_rdy_c,
...@@ -284,7 +284,7 @@ begin ...@@ -284,7 +284,7 @@ begin
-- generic map (g_counter_lgth => 4) -- generic map (g_counter_lgth => 4)
-- port map( -- port map(
-- uclk_i => uclk_i, -- uclk_i => uclk_i,
-- nfip_urst_i => nfip_urst_i, -- nfip_rst_i => nfip_rst_i,
-- reinit_counter_i => VAR3_RDY_i, -- reinit_counter_i => VAR3_RDY_i,
-- incr_counter_i => s_var3_rdy_incr_c, -- incr_counter_i => s_var3_rdy_incr_c,
-- counter_o => s_var3_rdy_c, -- counter_o => s_var3_rdy_c,
...@@ -307,7 +307,7 @@ begin ...@@ -307,7 +307,7 @@ begin
Refreshment_bit_Creation: process (uclk_i) Refreshment_bit_Creation: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_refreshment <= '0'; s_refreshment <= '0';
else else
......
wf_tx_serializer.vhd
View file @ 63cac757
...@@ -76,7 +76,7 @@ entity WF_tx_serializer is ...@@ -76,7 +76,7 @@ entity WF_tx_serializer is
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit -- Signal from the WF_reset_unit unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control -- Signals from the WF_engine_control
start_prod_p_i : in std_logic; --! indication that WF_engine_control is in prod_watchdog state start_prod_p_i : in std_logic; --! indication that WF_engine_control is in prod_watchdog state
...@@ -218,7 +218,7 @@ begin ...@@ -218,7 +218,7 @@ begin
Transmitter_FSM_Sync: process (uclk_i) Transmitter_FSM_Sync: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
tx_state <= idle; tx_state <= idle;
else else
tx_state <= nx_tx_state; tx_state <= nx_tx_state;
...@@ -405,7 +405,7 @@ crc_bytes_manc_encoder: WF_manch_encoder ...@@ -405,7 +405,7 @@ crc_bytes_manc_encoder: WF_manch_encoder
c_GENERATOR_POLY_length => 16) c_GENERATOR_POLY_length => 16)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_start_crc_p, start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p, data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd, data_bit_i => s_txd,
...@@ -431,7 +431,7 @@ crc_bytes_manc_encoder: WF_manch_encoder ...@@ -431,7 +431,7 @@ crc_bytes_manc_encoder: WF_manch_encoder
generic map(g_counter_lgth => 5) generic map(g_counter_lgth => 5)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
counter_top => s_bit_index_top, counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load, counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_index_p, counter_decr_p_i => s_decr_index_p,
...@@ -487,7 +487,7 @@ crc_bytes_manc_encoder: WF_manch_encoder ...@@ -487,7 +487,7 @@ crc_bytes_manc_encoder: WF_manch_encoder
bits_to_txd: WF_bits_to_txd bits_to_txd: WF_bits_to_txd
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i, nfip_rst_i => nfip_rst_i,
txd_bit_index_i => s_bit_index, txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch, data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch, crc_byte_manch_i => s_crc_bytes_manch,
...@@ -504,7 +504,7 @@ crc_bytes_manc_encoder: WF_manch_encoder ...@@ -504,7 +504,7 @@ crc_bytes_manc_encoder: WF_manch_encoder
Input_Byte_Sampling: process (uclk_i) Input_Byte_Sampling: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_urst_i = '1' then if nfip_rst_i = '1' then
s_byte <= (others => '0'); s_byte <= (others => '0');
else else
......
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