- pinout and iostd changes for v3

- synthesis with Synplify Premier (DFF triplication with the tmr attribute; RAM triplication "manually" on the code)

- pinout and iostd changes for v3
- synthesis with Synplify Premier (DFF triplication with the tmr attribute; RAM triplication "manually" on the code)
47350e02 · Evangelia Gousiou · e51c789c · 47350e02 · 47350e02 · 47350e02
Commit 47350e02 authored May 05, 2022 by Evangelia Gousiou
6 changed files
--- a/src/wf_dualram_512x8_clka_rd_clkb_wr.vhd
+++ b/src/wf_dualram_512x8_clka_rd_clkb_wr.vhd
@@ -25,19 +25,26 @@
 -- Authors      Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             |
 --              Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)                                 |
 -- Date         10/12/2010                                                                        |
+-- Version      v0.02                                                                             |
+-- Depends on   dualram_512x8.vhd                                                                 |
+----------------                                                                                  |
+-- Last changes                                                                                   |
+--     12/2010  v0.02  EG  code cleaned-up+commented                                              |
+--     11/2011  v0.03  EG  removed generics! addr+data lgth already defined at the                |
+--                         dualram_512x8                                                          |
 ---------------------------------------------------------------------------------------------------

 ---------------------------------------------------------------------------------------------------
--                                      SOLDERPAD LICENSE                                         |
--                                   Copyright CERN 2014-2018                                     |
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
 --                              ------------------------------------                              |
-- Copyright and related rights are licensed under the Solderpad Hardware License, Version 2.0    |
-- (the "License"); you may not use this file except in compliance with the License.              |
-- You may obtain a copy of the License at http://solderpad.org/licenses/SHL-2.0.                 |
-- Unless required by applicable law or agreed to in writing, software, hardware and materials    |
-- distributed under this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR       |
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language   |
-- governing permissions and limitations under the License.                                       |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
+-- version 2.1 of the License, or (at your option) any later version.                             |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
+-- See the GNU Lesser General Public License for more details.                                    |
+-- You should have received a copy of the GNU Lesser General Public License along with this       |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
 ---------------------------------------------------------------------------------------------------


@@ -86,6 +93,10 @@ architecture syn of wf_dualram_512x8_clka_rd_clkb_wr is

  signal s_one, s_rwB : std_logic;
  signal s_zeros      : std_logic_vector (7 downto 0);
+  
+  type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
+  signal s_data_o_A_array :   t_data_o_A_array (0 to 2);
+


 --=================================================================================================
@@ -100,7 +111,7 @@ begin
 ---------------------------------------------------------------------------------------------------
 -- Port A used for reading only, port B for writing only.

--  for triplication: G_memory_triplication: for I in 0 to 2 generate
+  G_memory_triplication: for I in 0 to 2 generate

    DualRam : dualram_512x8
    port map(
@@ -116,18 +127,18 @@ begin

      RESETn => s_one,

-      DOUTA  => data_porta_o, -- for triplication: s_data_o_A_array(I)
+      DOUTA  => s_data_o_A_array(I),
      DOUTB  => open);

--  end generate;
+  end generate;


 ---------------------------------------------------------------------------------------------------
 -- for triplication: Combinatorial Majority_Voter

-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
--                                                   (s_data_o_A_array(1) and s_data_o_A_array(2)) or
--                                                   (s_data_o_A_array(2) and s_data_o_A_array(0));
+Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
+                                (s_data_o_A_array(1) and s_data_o_A_array(2)) or
+                                (s_data_o_A_array(2) and s_data_o_A_array(0));

 end syn;
 --=================================================================================================

--- a/syn/Designer_Synpl_PaRscript.tcl
+++ b/syn/Designer_Synpl_PaRscript.tcl
+set my_project_dir [ file dirname [ file normalize [ info script ] ] ]
+puts $my_project_dir
+
+new_design -name "nanoFIP"  -family "ProASIC3" 
+
+
+set_device -die "A3P400" -speed "STD" -package "208 PQFP" -speed "STD" -voltage "1.5" -iostd "LVCMOS 2.5/5.0V" -temprange "COM" -voltrange "COM"
+
+import_source -merge_timing "yes" -format "EDIF" -edif_flavor "GENERIC" {nanofip.edn} -format "SDC" {Designer_Synpl_TimeConstr.sdc}
+
+compile
+
+create_clock -name {uclk_i} -period 25 uclk_i
+create_clock -name {wclk_i} -period 25 wclk_i
+
+import_aux -format "PDC" {.\Designer_Synpl_Pinout.pdc}
+
+layout -incremental "OFF"
+
+timer_get_clock_constraints -clock uclk_i
+timer_get_clock_constraints -clock wclk_i
+
+#close_design
\ No newline at end of file
--- a/syn/Designer_Synpl_Pinout.pdc
+++ b/syn/Designer_Synpl_Pinout.pdc
--- a/syn/Designer_Synpl_TimeConstr.sdc
+++ b/syn/Designer_Synpl_TimeConstr.sdc
+###################
+# Clocks
+###################
+
+create_clock { uclk_i } -name uclk_i -period 25.000000
+create_clock { wclk_i } -name wclk_i -period 25.000000
+create_clock -period 200.000000 -waveform {0.000000 100.000000} JTAG_controller/s_tck:Q
+
+##################
+# Input delays
+##################
+set_input_delay 10.000 -clock uclk_i {dat_i(*) fd_rxd_i fd_txer_i fd_wdgn_i rstin_i var1_acc_i var2_acc_i var3_acc_i}
+set_input_delay 10.000 -clock wclk_i {adr_i(*) cyc_i rst_i stb_i we_i}
+
+
+###################
+# Output delays
+###################
+set_output_delay 10.000 -clock uclk_i {dat_o(*) fd_rstn_o fd_txck_o fd_txd_o fd_txena_o r_fcser_o r_tler_o rston_o u_cacer_o u_pacer_o var1_rdy_o var2_rdy_o var3_rdy_o}
+set_output_delay 10.000 -clock wclk_i {ack_o}
--- a/syn/Synplify_Constraints.sdc
+++ b/syn/Synplify_Constraints.sdc
+#
+# Clocks
+#
+define_clock   { uclk_i } -name { uclk_i }  -period 25
+define_clock   { wclk_i } -name { wclk_i }  -period 25
+
+#
+# Attributes
+#
+define_attribute {reset_unit.rstin_st[0:4]} syn_encoding {safe, onehot}
+define_attribute {reset_unit.var_rst_st[0:5]} syn_encoding {safe, onehot}
+define_attribute {FIELDRIVE_Receiver.FIELDRIVE_Receiver_Deserializer.rx_st[0:5]} syn_encoding {safe, onehot}
+define_attribute {FIELDRIVE_Transmitter.tx_serializer.tx_st[0:6]} syn_encoding {safe, onehot}
+define_attribute {JTAG_controller.jc_st[0:3]} syn_encoding {safe, onehot}
+define_attribute {engine_control.control_st[0:9]} syn_encoding {safe, onehot}
+
+define_attribute {v:work.nanofip} {syn_radhardlevel} {tmr}
+
+### For TMR of the block RAMs check comments on the wf_dualram_512x8_clka_rd_clkb_wr.vhd file ### 
--- a/syn/Synplify_SynthesisScript.tcl
+++ b/syn/Synplify_SynthesisScript.tcl
+
+project -new
+
+#project files
+#set my_project_dir [get_env MY_PROJECT]
+#puts $::argv0
+set my_project_dir [ file dirname [ file normalize [ info script ] ] ]
+puts $my_project_dir
+
+add_file -vhdl -lib work "$my_project_dir/../src/dualram_512x8.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_package.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_dualram_512x8_clka_rd_clkb_wr.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_cons_bytes_processor.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_cons_outcome.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_consumption.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_rx_deglitcher.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_decr_counter.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_crc.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_rx_deserializer.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_incr_counter.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_rx_osc.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_fd_receiver.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_tx_osc.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_tx_serializer.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_fd_transmitter.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_model_constr_decoder.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_prod_bytes_retriever.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_prod_permit.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_status_bytes_gen.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_production.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_reset_unit.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_wb_controller.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_prod_data_lgth_calc.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_engine_control.vhd"
+add_file -vhdl -lib work "$my_project_dir/../src/wf_jtag_controller.vhd"
+add_file -vhdl -lib work "$my_project_dir/../top/nanofip.vhd"
+
+
+#implementation: "synthesis"
+impl -add synthesis -type fpga
+
+#device options
+set_option -technology ProASIC3
+set_option -part A3P400
+set_option -package PQFP208
+set_option -speed_grade Std
+
+#compilation/mapping options
+set_option -top_module "work.nanofip"
+
+# mapper_options
+set_option -frequency 40.000000
+
+# Actel 400K
+#set_option -run_prop_extract 1
+set_option -disable_io_insertion 0
+
+
+set_option -maxfan 10
+set_option -maxfan_hard 1 
+set_option -retiming 0
+set_option -resource_sharing 1
+
+set_option -default_enum_encoding onehot
+set_option -symbolic_fsm_compiler 1
+
+
+# Actel 500K
+#set_option -globalthreshold 50
+
+# Compiler Options
+
+
+
+#set result format/file last
+project -result_file "$my_project_dir/nanofip.edn"
+
+#design plan options
+set_option -nfilter_user_path ""
+impl -active "synthesis"
+
+
+# ###################
+# Constraints file
+# ##################
+add_file -constraint "$my_project_dir/synplify_constraints.sdc"
+
+
+project -run
+