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nanoFIP - Gateware
Commit 15122c97 authored by egousiou's avatar egousiou
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new unit WF_wb_controller.vhd 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@116 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 63cac757
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DualClkRAM.vhd
View file @ 15122c97
......@@ -49,10 +49,10 @@ use PROASIC3.all;
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! ProASIC3 lib \n
--! ProASIC3 lib \n
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......
NanoFip.pdc
View file @ 15122c97
......@@ -573,6 +573,8 @@ set_io r_fcser_o \
-pinname 85 \
-fixed yes \
-DIRECTION Output
#
# Non IO constraints
#
......
WF_wb_controller.vhd 0 → 100644
View file @ 15122c97
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_wb_controller.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_wb_controller --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to
--! the user's STBs.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 20/01/2011
--
--
--! @version v0.01
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_production \n
--! WF_consumption \n
--
---------------------------------------------------------------------------------------------------
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! \n\n<b>Last changes:</b>\n
--! ->
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 1, 3, 4 of var_i(0 to 6) are unused" --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_wb_controller
--=================================================================================================
entity WF_wb_controller is
port (
-- INPUTS
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_rst_i : in std_logic; --! WISHBONE reset
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_stb_r_edge_p_i : in std_logic; --! rising edge on WISHBONE strobe
wb_we_i : in std_logic; --! WISHBONE write enable
wb_adr_id_i : in std_logic_vector (2 downto 0); --! 3 first bits of WISHBONE address
-- OUTPUTS
-- Signal from the WF_production_unit
wb_ack_prod_p_o : out std_logic; --! response to a write cycle
-- latching moment of wb_dat_i
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_p_o : out std_logic --! WISHBONE acknowledge
-- response to master's strobe
);
end entity WF_wb_controller;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_ack_write_p_d, s_wb_ack_read_p_d : std_logic;
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Generate_wb_ack_write_p_o: Generation of the wb_ack_write_p signal
--! (acknowledgement from WISHBONE Slave of the write cycle, as a response to the master's storbe).
--! The 1 wb_clk-wide pulse is generated if the wb_cyc and wb_we are asserted and the WISHBONE input
--! address corresponds to an address in the Produced memory block.
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_id_i = "010") and
(wb_we_i = '1') and
(wb_cyc_i = '1'))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Generate_wb_ack_read_p: Generation of the wb_ack_read_p signal
--! (acknowledgement from WISHBONE Slave of the read cycle, as a response to the master's strobe).
--! The 1 wb_clk-wide pulse is generated if the wb_cyc is asserted and the WISHBONE input address
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_id_i(1 downto 0) = "00") and
(wb_cyc_i = '1'))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Output_Register:
WB_ACK: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then
s_wb_ack_read_p_d <= '0';
s_wb_ack_write_p_d <= '0';
else
s_wb_ack_read_p_d <= s_wb_ack_read_p;
s_wb_ack_write_p_d <= s_wb_ack_write_p;
end if;
end if;
end process;
wb_ack_p_o <= s_wb_ack_read_p_d or s_wb_ack_write_p_d;
wb_ack_prod_p_o <= s_wb_ack_write_p_d;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
nanofip.vhd
View file @ 15122c97
......@@ -99,6 +99,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_consumption and WF_production units.
--! o WF_model_constr_dec : for the decoding of the WorldFIP settings M_ID and C_ID and the
--! generation of the S_ID.
--! o WF_wb_controller : for the handling of the "User Interface WISHBONE Slave" control
--! signals.
--!
--! _____________ __________________________ _____________
--! | | | | | |
......@@ -116,9 +118,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! | | | | | | | WF_engine |
--! |_____________| | | | | | _control |
--! | | | | | |
--! _____________ | | | | | |
--! | | | WF_ | | WF_ | | |
--! _____________ | WF_ | | WF_ | | |
--! | | |consumption| | production | | |
--! | | | | | | | |
--! | WF_reset | | | | | | |
--! | _unit | | | | | | |
--! | | | | | | | |
......@@ -126,11 +128,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! | | | | | |
--! _____________ | | | | | |
--! | | | | | | | |
--! | | | | | | | |
--! | WF_model_ | | | | | | |
--! | constr_dec | | | | | | |
--! | | | | | | | |
--! |_____________| |___________| |____________| |_____________|
--! | | |___________| |____________| | |
--! | WF_model_ | | |
--! | constr_dec | ___________________________ | |
--! | | | WF_wb_controller | | |
--! |_____________| |___________________________| |_____________|
--!
--! Figure 3: nanoFIP block diagram
--!
......@@ -144,28 +146,29 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 15/01/2011
--! @date 15/01/2011
--
--
--! @version v0.04
--! @version v0.04
--
--
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_inputs_synchronizer \n
--! WF_reset_unit \n
--! WF_model_constr_dec \n
--! WF_tx_rx_osc \n
--! WF_consumption \n
--! WF_production \n
--! WF_engine_control \n
--! WF_inputs_synchronizer \n
--! WF_reset_unit \n
--! WF_model_constr_dec \n
--! WF_tx_rx_osc \n
--! WF_consumption \n
--! WF_production \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 30/06/2009 v0.010 EB First version \n
......@@ -173,7 +176,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 07/07/2009 v0.011 EB Comments \n
--! -> 15/09/2009 v0.v2 PA
--! -> 09/12/2010 v0.v3 EG Logic removed (new unit inputs_synchronizer added)
--! -> 01/2011 v0.04 EG main restructuring; only 7 units on top level
--! -> 7/01/2011 v0.04 EG major restructuring; only 7 units on top level
--! -> 20/01/2011 v0.05 EG new unit WF_wb_controller(removes the or gate from top level)
--
---------------------------------------------------------------------------------------------------
--
......@@ -273,9 +277,6 @@ entity nanofip is
-- User Interface, NON-WISHBONE
-- dat_o : out std_logic_vector(15 downto 8);--! Data out of stand-alone mode;
--! used in addition to dat_o(7 downto 0)
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
u_cacer_o : out std_logic; --! nanoFIP status byte, bit 2
......@@ -319,20 +320,19 @@ architecture struc of nanofip is
signal s_rst, s_rx_byte_ready, s_start_prod_p, s_rst_rx_osc, s_prod_request_byte_p : std_logic;
signal s_prod_byte_ready_p, s_prod_last_byte_p, s_rstin_f_edge, s_wb_we_synch : std_logic;
signal s_prod_last_byte_p : std_logic;
signal s_rstin_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch: std_logic;
signal s_fss_crc_fes_manch_ok_p, s_cons_fss_decoded_p, s_prod_ack, s_wb_ack_cons : std_logic;
signal s_fss_crc_fes_manch_ok_p, s_cons_fss_decoded_p : std_logic;
signal s_crc_wrong_p, s_reset_nFIP_and_FD_p, s_rx_manch_clk_p, s_rx_bit_clk_p : std_logic;
signal s_var1_access_synch, s_var2_access_synch, s_var3_access_synch, s_wb_stb_synch : std_logic;
signal s_var1_rdy, s_var2_rdy, s_var3_rdy, s_ack_o, s_assert_RSTON_p : std_logic;
signal s_rst_rx_unit_p, s_nfip_status_r_tler, s_signif_edge_window : std_logic;
signal s_var1_rdy, s_var2_rdy, s_var3_rdy, s_assert_RSTON_p, s_wb_ack_prod : std_logic;
signal s_rst_rx_unit_p, s_nfip_status_r_tler, s_signif_edge_window , s_wb_we_synch : std_logic;
signal s_fd_rxd_synch, s_fd_rxd_edge_p, s_fd_rxd_r_edge_p, s_fd_rxd_f_edge_p : std_logic;
signal s_wb_stb_r_edge, s_adjac_bits_window, s_wb_cyc_synch : std_logic;
signal s_wb_stb_r_edge, s_adjac_bits_window, s_wb_cyc_synch, s_prod_byte_ready_p : std_logic;
signal s_var_from_control : t_var;
signal s_data_length_from_control, s_subs_synch, s_wb_dati_synch : std_logic_vector (7 downto 0);
signal s_data_length_from_control, s_subs_synch : std_logic_vector (7 downto 0);
signal s_rx_byte, s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_cons_prod_byte_index_from_control : std_logic_vector (7 downto 0);
signal s_wb_adri_synch : std_logic_vector (9 downto 0);
signal s_slone_dati_synch : std_logic_vector(15 downto 0);
signal s_m_id_synch, s_c_id_synch : std_logic_vector (3 downto 0);
signal s_p3_lgth_synch : std_logic_vector (2 downto 0);
......@@ -365,7 +365,6 @@ begin
wb_cyc_a_i => cyc_i,
wb_we_a_i => we_i,
wb_stb_a_i => stb_i,
wb_adr_a_i => adr_i,
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
......@@ -377,7 +376,6 @@ begin
p3_lgth_a_i => p3_lgth_i,
---------------------------------------------------------
rstin_o => s_rstin_synch,
rstin_f_edge_o => s_rstin_f_edge,
slone_o => s_slone_synch,
nostat_o => s_nostat_synch,
fd_wdgn_o => s_fd_wdgn_synch,
......@@ -390,8 +388,6 @@ begin
wb_we_o => s_wb_we_synch,
wb_stb_o => s_wb_stb_synch,
wb_stb_r_edge_o => s_wb_stb_r_edge,
wb_dati_o => s_wb_dati_synch,
wb_adri_o => s_wb_adri_synch,
var1_access_o => s_var1_access_synch,
var2_access_o => s_var2_access_synch,
var3_access_o => s_var3_access_synch,
......@@ -413,7 +409,6 @@ begin
port map(
uclk_i => uclk_i,
rstin_i => s_rstin_synch,
rstin_f_edge_i => s_rstin_f_edge,
rstpon_i => rstpon_i,
rate_i => s_rate_synch,
var_i => s_var_from_control,
......@@ -465,9 +460,7 @@ begin
fd_rxd_r_edge_p_i => s_fd_rxd_r_edge_p,
fd_rxd_f_edge_p_i => s_fd_rxd_f_edge_p,
wb_clk_i => wclk_i,
wb_adr_i => s_wb_adri_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
wb_cyc_i => s_wb_cyc_synch,
wb_adr_i => adr_i (8 downto 0),
var_i => s_var_from_control,
byte_index_i => s_cons_prod_byte_index_from_control,
rst_rx_unit_p_i => s_rst_rx_unit_p,
......@@ -479,7 +472,6 @@ begin
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
data_o => dat_o,
wb_ack_cons_p_o => s_wb_ack_cons,
byte_o => s_rx_byte,
byte_ready_p_o => s_rx_byte_ready,
fss_received_p_o => s_cons_fss_decoded_p,
......@@ -504,11 +496,9 @@ begin
nostat_i => nostat_i,
nfip_rst_i => s_rst,
wb_clk_i => wclk_i,
wb_data_i => s_wb_dati_synch,
wb_adr_i => s_wb_adri_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
wb_we_i => s_wb_we_synch,
wb_cyc_i => s_wb_cyc_synch,
wb_data_i => dat_i(7 downto 0),
wb_adr_i => adr_i(8 downto 0),
wb_ack_prod_p_i => s_wb_ack_prod,
slone_data_i => s_slone_dati_synch,
var1_acc_i => s_var1_access_synch,
var2_acc_i => s_var2_access_synch,
......@@ -519,7 +509,7 @@ begin
data_length_i => s_data_length_from_control,
byte_index_i => s_cons_prod_byte_index_from_control,
start_prod_p_i => s_start_prod_p,
byte_ready_p_i => s_prod_byte_ready_p,
byte_request_accept_p_i => s_prod_byte_ready_p,
last_byte_p_i => s_prod_last_byte_p,
nfip_status_r_tler_i => s_nfip_status_r_tler,
nfip_status_r_fcser_p_i => s_crc_wrong_p,
......@@ -529,15 +519,14 @@ begin
model_id_dec_i => s_model_id_dec,
constr_id_dec_i => s_constr_id_dec,
---------------------------------------------------------
request_byte_p_o => s_prod_request_byte_p,
byte_request_p_o => s_prod_request_byte_p,
tx_data_o => fd_txd_o,
tx_enable_o => fd_txena_o,
u_cacer_o => u_cacer_o,
u_pacer_o => u_pacer_o,
r_tler_o => r_tler_o,
r_fcser_o => r_fcser_o,
var3_rdy_o => s_var3_rdy,
wb_ack_prod_p_o => s_prod_ack
var3_rdy_o => s_var3_rdy
---------------------------------------------------------
);
......@@ -551,27 +540,27 @@ begin
generic map( c_QUARTZ_PERIOD => c_QUARTZ_PERIOD)
port map(
uclk_i => uclk_i,
nfip_rst_i => s_rst,
tx_request_byte_p_i => s_prod_request_byte_p,
rx_fss_received_p_i => s_cons_fss_decoded_p,
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready,
uclk_i => uclk_i,
nfip_rst_i => s_rst,
tx_byte_request_p_i => s_prod_request_byte_p,
rx_fss_received_p_i => s_cons_fss_decoded_p,
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready,
rx_fss_crc_fes_manch_ok_p_i => s_fss_crc_fes_manch_ok_p,
rx_crc_wrong_p_i => s_crc_wrong_p,
rate_i => s_rate_synch,----------------
subs_i => s_subs_synch,----------------
p3_lgth_i => s_p3_lgth_synch, ----------------------
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
rx_crc_wrong_p_i => s_crc_wrong_p,
rate_i => s_rate_synch,
subs_i => s_subs_synch,
p3_lgth_i => s_p3_lgth_synch,
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
---------------------------------------------------------
var_o => s_var_from_control,
tx_start_prod_p_o => s_start_prod_p ,
tx_byte_ready_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control,
prod_data_length_o => s_data_length_from_control,
rst_rx_unit_p_o => s_rst_rx_unit_p
var_o => s_var_from_control,
tx_start_prod_p_o => s_start_prod_p ,
tx_byte_request_accept_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control,
prod_data_length_o => s_data_length_from_control,
rst_rx_unit_p_o => s_rst_rx_unit_p
---------------------------------------------------------
);
......@@ -588,7 +577,7 @@ begin
port map(
uclk_i => uclk_i,
nfip_rst_i => s_rst,
model_id_i => s_m_id_synch,--------------
model_id_i => s_m_id_synch,
constr_id_i => s_c_id_synch,
---------------------------------------------------------
select_id_o => s_id_o,
......@@ -600,9 +589,22 @@ begin
---------------------------------------------------------------------------------------------------
-- WF_wb_controller --
---------------------------------------------------------------------------------------------------
WISHBONE_ack_generator: WF_wb_controller
port map (
wb_clk_i => wclk_i,
wb_rst_i => rst_i,
wb_cyc_i => s_wb_cyc_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
wb_we_i => s_wb_we_synch,
wb_adr_id_i => adr_i (9 downto 7),
---------------------------------------------------------------
wb_ack_prod_p_o => s_wb_ack_prod,
wb_ack_p_o => ack_o
---------------------------------------------------------------
);
ack_o <= (s_prod_ack or s_wb_ack_cons); --and stb_i;
s_ack_o <= s_prod_ack or s_wb_ack_cons;
---------------------------------------------------------------------------------------------------
......@@ -614,4 +616,4 @@ end architecture struc;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------=========================
\ No newline at end of file
---------------------------------------------------------------------------------------------------
\ No newline at end of file
tmp_snippets.txt deleted 100644 → 0
View file @ 63cac757
--3456789-123456789-123456789-123456789-123456789-123456789-123456789-123456789
--! test for parity
component PARITY
port (A: in std_logic_vector (7 downto 0); --! test for parity: input byte
ODD: out std_logic); --! output bit
end component;
--! Architecture contains only connectivity
architecture struc of nanofip is
begin
--! It should be documented now
par1: PARITY --! my dummy parity to let block appear
port map (); --! I think it's documented now
end par1;
end a1;
-------------------------------------------------------------------------------
-- E N D O F F I L E
-------------------------------------------------------------------------------
tmp_wf_reset_unit_with_PoR.vhd deleted 100644 → 0
View file @ 63cac757
--=================================================================================================
--! @file WF_reset_unit.vhd
--=================================================================================================
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
---------------------------------------------------------------------------------------------------
-- --
-- WF_reset_unit --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: WF_reset_unit
--
--! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset
--! and user interface reset (RSTON)
--
--
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 08/2010
--
--
--! @version v0.02
--
--
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_cons_bytes_from_rx\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 07/2009 v0.01 EB First version \n
--! 08/2010 v0.02 EG checking of bytes1 and2 of reset var added \n
--! fd_rstn_o, nFIP_rst_o enabled only if rstin has been active for > 16 uclk \n
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_reset_unit
--=================================================================================================
entity WF_reset_unit is
port (
-- INPUTS
-- User Interface general signals (synchronized) (after synchronization)
uclk_i : in std_logic; --! 40 MHz clock
urst_i : in std_logic; --! initialisation control, active low
urst_r_edge_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding
rate_i : in std_logic_vector (1 downto 0);
-- Signal from the central control unit WF_engine_control
var_i : in t_var; --! variable type
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
-- OUTPUTS
-- nanoFIP internal reset
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
-- nanoFIP output to the User Interface
rston_o : out std_logic; --! reset output, active low
-- nanoFIP output to FIELDRIVE
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
);
end entity WF_reset_unit;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_reset_unit is
signal s_intern_rst : std_logic;
signal s_urst_c_is_eight, s_reinit_counter, s_FD_rst : std_logic;
signal s_urst_c_is_full, s_urst_c_is_ten, s_incr_counter : std_logic;
signal s_urst_c_is_two, s_RSTON_counter_is_full : std_logic;
signal s_RSTON_counter : unsigned (1 downto 0);
signal s_counter : unsigned(C_PERIODS_COUNTER_LENGTH-1 downto 0)
:= (others=>'0'); -- init for simulation
type rstin_st_t is (idle, rstin_eval, intern_rst_ON_FD_rst_ON,intern_rst_OFF_FD_rst_ON);
signal rstin_st, nx_rstin_st : rstin_st_t;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process s_rst_creation: the process follows the input signal rstin
--! and confirms that it stays active for more than 2^(C_RSTIN_C_LGTH-1) uclk cycles;
--! If so, it enables the signal s_intern_rst to follow it.
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Receiver_FSM_Sync: storage of the current state of the FSM
RSTIN_FSM_Sync: process(uclk_i)
begin
if rising_edge(uclk_i) then
-- if urst_i = '0' then --has to be the PoR; otherwise i ll always be sent to idle (coundn t count the 40cycles for ex)---------
-- rstin_st <= idle;
-- else
rstin_st <= nx_rstin_st;
-- end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process RSTIN_FSM_Comb_State_Transitions:
--! definition of the state transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st,var_i,rst_nFIP_and_FD_p_i,urst_r_edge_i,
s_urst_c_is_two,urst_i,s_urst_c_is_eight,
s_urst_c_is_ten, s_urst_c_is_full)
begin
nx_rstin_st <= idle;
case rstin_st is
when idle =>
if var_i = var_rst then
if rst_nFIP_and_FD_p_i = '1' then
nx_rstin_st <= intern_rst_ON_FD_rst_ON;
else
nx_rstin_st <= idle;
end if;
else
if urst_r_edge_i = '1' then -- rising edges of reset move the FSM to the next state,
nx_rstin_st <= rstin_eval;-- so as not to be getting stuck if the reset is stuck
else
nx_rstin_st <= idle;
end if;
end if;
when rstin_eval =>
if urst_i = '0' then
nx_rstin_st <= idle;
else
if s_urst_c_is_eight = '1' then
nx_rstin_st <= intern_rst_ON_FD_rst_ON;
else
nx_rstin_st <= rstin_eval;
end if;
end if;
when intern_rst_ON_FD_rst_ON =>
if var_i = var_rst then
if s_urst_c_is_two ='1' then
nx_rstin_st <= intern_rst_OFF_FD_rst_ON;
else
nx_rstin_st <= intern_rst_ON_FD_rst_ON;
end if;
else
if s_urst_c_is_ten ='1' then
nx_rstin_st <= intern_rst_OFF_FD_rst_ON;
else
nx_rstin_st <= intern_rst_ON_FD_rst_ON;
end if;
end if;
when intern_rst_OFF_FD_rst_ON =>
if s_urst_c_is_full ='1' then
nx_rstin_st <= idle;
else
nx_rstin_st <= intern_rst_OFF_FD_rst_ON;
end if;
when others =>
nx_rstin_st <= idle;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process RSTIN_FSM_Comb_Output_Signals:
--! definition of the output signals of the FSM
RSTIN_FSM_Comb_Output_Signals: process (rstin_st, urst_i)
begin
case rstin_st is
when idle =>
s_reinit_counter <= '1'; -- counter initialized
s_intern_rst <= '0';
s_FD_rst <= '0';
s_incr_counter <= '0';
when rstin_eval =>
s_reinit_counter <= '0'; -- counting (until 8)
s_intern_rst <= '0'; -- the urst_i signal
s_FD_rst <= '0';
s_incr_counter <= urst_i;
when intern_rst_ON_FD_rst_ON =>
s_reinit_counter <= '0'; -- free counter continuing counting 2 uclk periods
s_intern_rst <= '1';
s_FD_rst <= '1';
s_incr_counter <= '1';
when intern_rst_OFF_FD_rst_ON =>
s_reinit_counter <= '0'; -- free counter continuing counting (until counter full)
s_intern_rst <= '0';
s_FD_rst <= '1';
s_incr_counter <= '1';
when others =>
s_reinit_counter <= '1';
s_intern_rst <= '0';
s_FD_rst <= '0';
s_incr_counter <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- used for the evaluation of the RSTIN signal, also for counting 2 clock cycles the internal rest,
-- & ...clock cycles the fieldrive reset.
counter: WF_incr_counter
generic map (counter_length => C_PERIODS_COUNTER_LENGTH)
port map(
uclk_i => uclk_i,
nFIP_urst_i => '0' , --has to be the PoR--------------
reinit_counter_i => s_reinit_counter,
incr_counter_i => s_incr_counter,
counter_o => s_counter,
counter_is_full_o => s_urst_c_is_full);
s_urst_c_is_two <= '1' when s_counter = to_unsigned(2, s_counter'length)
else '0';
s_urst_c_is_ten <= '1' when s_counter = to_unsigned(10, s_counter'length)
else '0';
s_urst_c_is_eight <= '1' when s_counter = to_unsigned(8, s_counter'length)
else '0';
s_urst_c_is_ten <= '1' when s_counter = to_unsigned(10, s_counter'length)
else '0';
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process RSTON_generator: Generation of the RSTON signal that is enabled when
--! at the end of a valid consumed frame of a reset variable, where the 2nd data byte contains
--! the station's address. The signal stays enabled for four cycles.
---------------------------------------------------------------------------------------------------
RSTON_generator: process(uclk_i)
begin
if rising_edge(uclk_i) then
if s_intern_rst = '1' then
rston_o <= '1';
else
if assert_RSTON_p_i = '1' then -- activation after the pulse that indicates that
rston_o <= '0'; -- a valid consumed frame has arrived with its 2nd
end if; -- data byte containing the station's address.
if s_RSTON_counter_is_full = '1' then -- deactivation after 4 clock cycles
rston_o <= '1';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RSTON_free_counter: WF_incr_counter
generic map (counter_length => 2)
port map(
uclk_i => uclk_i,
nFIP_urst_i => s_intern_rst,
reinit_counter_i => assert_RSTON_p_i,
incr_counter_i => '1',
counter_o => s_RSTON_counter,
counter_is_full_o => s_RSTON_counter_is_full
);
---------------------------------------------------------------------------------------------------
--! nFIP_rst_o: nanoFIP internal reset, active high;
--! fd_rstn_o : FIELDRIVE reset, active low;
--! They are both activated by the signals:
--! Signal |Stays active for (Uclk cycles) |Constraint
--!------------------------------------------------------------------------------------------------
--! PoR |full PoR duration |No
--! RSTIN |2 |RSTIN active > 8 uclk cycles
--! s_rst_nFIP_and_FD |2 |No
nFIP_and_FD_Resets: process (uclk_i)
begin
if rising_edge(uclk_i) then
nFIP_rst_o <= s_intern_rst or s_intern_rst; -- or PoR
fd_rstn_o <= not (s_intern_rst or s_FD_rst); -- or PoR
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ 15122c97
......@@ -46,11 +46,11 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! DualClkRAM.vhd \n
--! DualClkRAM.vhd \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_bits_to_txd.vhd
View file @ 15122c97
......@@ -46,13 +46,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_tx_rx_osc \n
--! WF_tx_serializer \n
--! WF_reset_unit \n
--! WF_tx_rx_osc \n
--! WF_tx_serializer \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -142,7 +142,7 @@ begin
if tx_clk_p_i = '1' then
if sending_fss_i = '1' then
txd_o <= FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize)
txd_o <= c_FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize)
elsif sending_data_i = '1' then
txd_o <= data_byte_manch_i (to_integer (resize(txd_bit_index_i, 4))); -- 1 data-byte
......@@ -151,7 +151,7 @@ begin
txd_o <= crc_byte_manch_i (to_integer (txd_bit_index_i)); -- CRC: 2 bytes long
elsif sending_fes_i = '1' then
txd_o <= FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
else
txd_o <= '0';
......@@ -179,10 +179,10 @@ begin
if ((sending_fss_i = '1') or (sending_data_i = '1') or -- tx sending bits
(sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then
if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enabble with the
end if; -- the delivery of the 1st FSS bit
-- txd :________|-----|___________|--------
if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enabble with the
end if; -- the delivery of the 1st FSS bit
-- txd (FSS) :________|-----|___________|--------
-- tx_clk_p_buff(1):______|-|___|-|___|-|___|-|___|-|__
-- sending_FSS :___|-------------------------------
-- tx_enable :________|--------------------------
......
wf_cons_bytes_processor.vhd
View file @ 15122c97
......@@ -61,24 +61,25 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 15/12/2010
--! @date 15/12/2010
--
--
--! @version v0.03
--! @version v0.03
--
--
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_engine_control \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/09/2009 v0.01 EB First version \n
......@@ -119,11 +120,9 @@ port (
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address to memory
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_stb_r_edge_p_i : in std_logic; --! pulse on the rising edge of stb_i
wb_adr_i : in std_logic_vector (8 downto 0); --! WISHBONE address to memory
-- Signals from the WF_rx_deserializer unit
byte_i : in std_logic_vector (7 downto 0); --! input byte
......@@ -138,9 +137,8 @@ port (
-- OUTPUTS
-- nanoFIP User Interface, WISHBONE Slave outputs
-- nanoFIP User Interface, WISHBONE Slave output
data_o : out std_logic_vector (15 downto 0);--! data out bus
wb_ack_cons_p_o : out std_logic; --! WISHBONE acknowledge
-- Signals to the WF_cons_frame_validator unit
cons_ctrl_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT Control byte
......@@ -203,18 +201,6 @@ begin
data_portb_i => byte_i, -- byte to be written
write_en_portb_i => s_write_byte_to_mem_p ); -- write enable
---------------------------------------------------------------------------------------------------
--!@brief Generate_wb_ack_cons_p_o: Generation of the wb_ack_cons_p_o signal
--! (acknowledgement from WISHBONE Slave of the read cycle, as a response to the master's strobe).
--! wb_ack_cons_p_o is 1 wclk-wide pulse asserted 3 wclk cycles after the assertion of the
--! asynchronous strobe signal, if the wb_cyc is asserted and the WISHBONE input address
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_cons_p_o: wb_ack_cons_p_o <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 8) = "00") and
(wb_cyc_i = '1'))
else '0';
---------------------------------------------------------------------------------------------------
......
wf_cons_bytes_to_dato.vhd
View file @ 15122c97
......@@ -51,12 +51,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_cons_bytes_processor \n
--! WF_reset_unit \n
--! WF_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_cons_outcome.vhd
View file @ 15122c97
......@@ -46,11 +46,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_enginr_control \n
--! WF_cons_frame_validator \n
--! WF_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_consumption.vhd
View file @ 15122c97
......@@ -27,48 +27,52 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit gathers the main actions that regard data consumption.
--! @brief The unit groups the main actions that regard data consumption.
--! It instantiates the units:
--!
--! o WF_rx_deglitcher : for the filtering of the "nanoFIP FIELDRIVE"
--! input fd_rxd
--! o WF_rx_deserializer : for the creation of bytes of data
--! o WF_cons_bytes_processor : for the manipulation of the data as they arrive (mainly
--!
--! o WF_rx_deserializer : for the formation of bytes of data
--!
--! o WF_cons_bytes_processor : for the handling of the data as they arrive (mainly
--! registering them to the RAM or putting them to DAT_O)
--!
--! o WF_cons_frame_validator : for the validation of the consumed frame, at the end of
--! of its arrival (in terms of FSS, Ctrl, PDU_TYPE, Lgth,
--! CRC bytes & manch. encoding)
--!
--! o WF_cons_outcome : for the generation of the "nanoFIP User Interface, NON-
--! WISHBONE" outputs VAR1_RDY and VAR2_RDY (for var_1, var_2)
--! or of the internal signals for the nanoFIP and FIELDRIVE
--! resets (for a var_rst)
--!
--! __ _________________________________
--! | | |
--! | | WF_cons_outcome |
--! | |_________________________________|
--! Level 2 ^
--! | _________________________________
--! | | |
--! | | WF_cons_frame_validator |
--! |__ |_________________________________|
--! _________________________________
--! | |
--! | WF_cons_outcome |
--! |_________________________________|
--! ^
--! __ _________________________________
--! | | |
--! Level 1 | WF_cons_bytes_processor |
--! | | |
--! |__ |_________________________________|
--! _________________________________
--! | |
--! | WF_cons_frame_validator |
--! |_________________________________|
--! ^
--! __ _________________________________
--! | | |
--! | | WF_rx_deserializer |
--! | | |
--! | |_________________________________|
--! Level 0 ^
--! | _________________________________
--! | | |
--! | | WF_rx_deglitcher |
--! |__ |_________________________________|
--! _________________________________
--! | |
--! | WF_cons_bytes_processor |
--! | |
--! |_________________________________|
--! ^
--! _________________________________
--! | |
--! | WF_rx_deserializer |
--! | |
--! |_________________________________|
--! ^
--! _________________________________
--! | |
--! | WF_rx_deglitcher |
--! |_________________________________|
--!
--! _______________________________________________________________
--! 0__________________________FIELDBUS____________________________O
......@@ -91,20 +95,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_prod_bytes_retriever \n
--! WF_status_bytes_gen \n
--! WF_tx_serializer \n
--! WF_engine_control \n
--! WF_prod_bytes_retriever \n
--! WF_status_bytes_gen \n
--! WF_tx_serializer \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! ->
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo
......@@ -163,12 +166,10 @@ entity WF_consumption is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector(9 downto 0);
wb_cyc_i : in std_logic;
wb_stb_r_edge_p_i : in std_logic;
wb_adr_i : in std_logic_vector(8 downto 0);
-- used by: WF_cons_bytes_processor for the managment of the Consumption RAM
......@@ -207,7 +208,6 @@ entity WF_consumption is
-- nanoFIP User Interface, WISHBONE Slave outputs
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
-- Signals to the WF_engine_control
byte_o : out std_logic_vector (7 downto 0);
......@@ -239,7 +239,7 @@ end entity WF_consumption;
architecture struc of WF_consumption is
signal s_rxd_filtered, s_rxd_filtered_f_edge_p, s_cons_frame_ok_p, s_crc_wrong_p : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p, s_fss_crc_fes_manch_ok_p, s_byte_ready_p : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p, s_fss_crc_fes_manch_ok_p, s_byte_ready_p: std_logic;
signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0);
signal s_byte_from_rx : std_logic_vector (7 downto 0);
......@@ -256,7 +256,7 @@ begin
--! @brief Instantiation of the WF_rx_deglitcher unit that applies a glitch filter to the "nanoFIP
--! FIELDRIVE" input signal fd_rxd.
Consumption_Level_0_Deglitcher : WF_rx_deglitcher
Consumption_Deglitcher : WF_rx_deglitcher
generic map (c_DEGLITCH_LGTH => 10)
port map(
uclk_i => uclk_i,
......@@ -278,7 +278,7 @@ begin
--! @brief Instantiation of the WF_rx_deserializer unit that deserializes the deglitched fd_rxd
--! and constructs bytes of data.
Consumption_Level_0_Deserializer: WF_rx_deserializer
Consumption_Deserializer: WF_rx_deserializer
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......@@ -308,7 +308,7 @@ begin
--! arriving from the WF_rx_deserializer, by registering them to the Consumed memories or by
--! transferring them to the "nanoFIP User Interface, NON_WISHBONE" output bus DAT_O.
Consumption_Level_1_bytes_processor : WF_cons_bytes_processor
Consumption_Bytes_Processor : WF_cons_bytes_processor
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......@@ -319,10 +319,7 @@ begin
byte_i => s_byte_from_rx,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
wb_stb_r_edge_p_i => wb_stb_r_edge_p_i,
wb_cyc_i => wb_cyc_i,
-------------------------------------------------
wb_ack_cons_p_o => wb_ack_cons_p_o,
data_o => data_o,
cons_ctrl_byte_o => s_cons_ctrl_byte,
cons_pdu_byte_o => s_cons_pdu_byte,
......@@ -339,7 +336,7 @@ begin
--! received RP_DAT frame with respect to the correctness of the Control, PDU_TYPE and Length
--! bytes of the Manchester encoding.
Consumption_Level_2_Frame_Validator: WF_cons_frame_validator
Consumption_Frame_Validator: WF_cons_frame_validator
port map(
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_pdu_byte,
......@@ -361,7 +358,7 @@ begin
--! the "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY & VAR2_RDY (for a var_1/2)
--! or the nanoFIP internal signals rst_nFIP_and_FD_p and assert_RSTON_p (for a var_rst).
Consumption_Level_2_Outcome : WF_cons_outcome
Consumption_Outcome : WF_cons_outcome
port map (
uclk_i => uclk_i,
slone_i => slone_i,
......
wf_crc.vhd
View file @ 15122c97
......@@ -45,14 +45,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_tx_serializer \n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_tx_serializer \n
--
--
--! \n<b>Modified by:</b> \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_engine_control.vhd
View file @ 15122c97
......@@ -72,12 +72,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_production \n
--! WF_consumption \n
--
--
--! \n<b>Modified by:</b> \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -117,37 +120,40 @@ entity WF_engine_control is
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
uclk_i : in std_logic; --! 40 MHz clock
nostat_i : in std_logic; --!if negated,nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings (synchronized with uclk)
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
subs_i : in std_logic_vector (7 downto 0); --! subscriber number coding
p3_lgth_i : in std_logic_vector (2 downto 0);--! produced var user-data length
rate_i : in std_logic_vector (1 downto 0);--! WorldFIP bit rate
subs_i : in std_logic_vector (7 downto 0);--! subscriber number coding
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_production
-- Signal from the WF_tx_serializer unit
tx_request_byte_p_i : in std_logic; --!
tx_byte_request_p_i : in std_logic; --! used for the counting of the
--! # produced bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_consumption
-- Signals from the WF_rx_deserializer unit
rx_byte_i : in std_logic_vector(7 downto 0);--!deserialized ID_DAT or RP_DAT byte
rx_byte_ready_p_i : in std_logic; --! indication of a new byte on rx_byte_i
rx_fss_crc_fes_manch_ok_p_i : in std_logic; --! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC (pulse after FES arrival)
rx_fss_received_p_i : in std_logic; --! pulse after a correct FSS detection (ID/ RP_DAT)
rx_byte_i : in std_logic_vector(7 downto 0);--!deserialized ID_DAT/ RP_DAT byte
rx_byte_ready_p_i : in std_logic;--! indication of a new byte on rx_byte_i
rx_fss_crc_fes_manch_ok_p_i: in std_logic; --! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC (pulse after FES arrival)
rx_fss_received_p_i : in std_logic; --! pulse after a correct FSS detection (ID/ RP_DAT)
......@@ -158,36 +164,36 @@ entity WF_engine_control is
-- Signals to the WF_production
-- Signal to the WF_tx_serializer unit
tx_byte_ready_p_o : out std_logic;--!
tx_last_byte_p_o : out std_logic;--! indication that it is the last data-byte
tx_start_prod_p_o : out std_logic;--! launches the transmitters's FSM
tx_byte_request_accept_p_o : out std_logic;--!
tx_last_byte_p_o : out std_logic;--! indication that it is the last data-byte
tx_start_prod_p_o : out std_logic;--! launches the transmitters's FSM
-- Signal to the WF_prod_bytes_retriever
prod_data_length_o : out std_logic_vector (7 downto 0); --! # bytes of the Conrol & Data
--! fields of a prod RP_DAT frame
prod_data_length_o : out std_logic_vector (7 downto 0);--! # bytes of the Conrol & Data
--!fields of a prod RP_DAT frame
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_consumption
-- Signal to the WF_rx_deserializer
rst_rx_unit_p_o : out std_logic;--!if an FES has not arrived after 8 bytes of an ID_DAT
--! or after 134 bytes of an RP_DAT, the state machine
--! of the WF_rx_deserializer unit returns to idle state
rst_rx_unit_p_o : out std_logic;--!if a FES hasn't arrived after 8 bytes of an ID_DAT
--!or after 134 bytes of a RP_DAT, the state machine
--!of the WF_rx_deserializer returns to idle state
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production & WF_consumption
-- Signal to the WF_cons_bytes_processor, WF_prod_bytes_retriever
prod_cons_byte_index_o : out std_logic_vector (7 downto 0);
prod_cons_byte_index_o : out std_logic_vector (7 downto 0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production, WF_consumption, WF_reset_unit
-- Signal to the WF_cons_bytes_processor, WF_prod_bytes_retriever, WF_reset_unit
var_o : out t_var --! variable received by a valid ID_DAT frame
--! that concerns this station
var_o : out t_var --! variable received by a valid ID_DAT frame
--! that concerns this station
);
end entity WF_engine_control;
......@@ -210,10 +216,10 @@ architecture rtl of WF_engine_control is
signal s_time_c_is_zero, s_broadcast_var, s_tx_start_prod_p, s_inc_rx_bytes_counter : std_logic;
signal s_producing, s_consuming, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_cons_wait_FSS : std_logic;
signal s_prod_data_length_match, s_tx_byte_ready_p, s_prod_wait_turnar_time : std_logic;
signal s_tx_byte_ready_p_d1, s_load_time_counter, s_tx_byte_ready_p_d2 : std_logic;
signal s_prod_data_length_match, s_tx_byte_request_accept_p, s_prod_wait_turnar_time : std_logic;
signal s_tx_byte_request_accept_p_d1, s_load_time_counter, s_prod_time_over : std_logic;
signal s_rst_rx_bytes_counter, s_tx_last_byte_p_d, s_tx_last_byte_p : std_logic;
signal s_id_dat_subs_byte, s_id_dat_frame_ok : std_logic;
signal s_id_dat_subs_byte, s_id_dat_frame_ok, s_tx_byte_request_accept_p_d2 : std_logic;
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
signal s_time_counter_top, s_time_c, s_turnaround_time, s_silence_time : unsigned(14 downto 0);
signal s_prod_data_length, s_tx_byte_index, s_rx_byte_index : std_logic_vector (7 downto 0);
......@@ -344,7 +350,7 @@ begin
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_produce_or_consume = "01") then
nx_control_st <= consume_wait_FSS; -- CRC & FES check ok! station has to consume
elsif (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber----->2----------------
nx_control_st <= idle; -- byte, a FES has not been detected
-- s_rx_bytes_c: starts counting at this state
......@@ -382,9 +388,9 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume =>
if (rx_fss_crc_fes_manch_ok_p_i = '1') or-- the cons RP_DAT frame arrived to the end,as expected
(rx_crc_wrong_p_i = '1') or -- FES detected but wrong CRC or manch. encoding
(s_rx_bytes_c > 130) then -- no FES detected after the max number of bytes
if (rx_fss_crc_fes_manch_ok_p_i = '1') or -- the cons frame arrived to the end,as expected
(rx_crc_wrong_p_i = '1') or -- FES detected but wrong CRC or manch. encoding
(s_rx_bytes_c > 130) then -- no FES detected after the max number of bytes
nx_control_st <= idle; -- back to idle
......@@ -553,6 +559,8 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- Counters for the number of bytes being received or produced --
---------------------------------------------------------------------------------------------------
......@@ -576,7 +584,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_incr_counter for the counting of the number of the bytes that are
--! being produced. The counter is reset at the "produce_wait_turnar_time" state of the FSM and
--! counts bytes following the "tx_request_byte_p_i" pulse in the "produce" state.
--! counts bytes following the "tx_byte_request_p_i" pulse in the "produce" state.
Produced_Bytes_Counter: WF_incr_counter
generic map(g_counter_lgth => 8)
......@@ -595,6 +603,21 @@ begin
-- when s_prod_data_length bytes have been counted,the signal s_prod_data_length_match is activated
s_prod_data_length_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_length) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_incr_counter for the counting of the production time.
Produced_Time_Counter: WF_incr_counter
generic map(g_counter_lgth => 18)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => s_rst_prod_bytes_counter,
incr_counter_i => '1',
-------------------------------------------------------
counter_o => open,
counter_is_full_o => s_prod_time_over
-------------------------------------------------------
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_incr_counter for the counting of the number of bytes that are
......@@ -626,7 +649,7 @@ begin
--! the signals reinit_counter_i and incr_counter_i of the Produced_Bytes_Counter and
--! Rx_Bytes_Counter according to the state of the FSM.
Arguments_For_Both_Bytes_Counters: process (s_id_dat_frame_ok, s_consuming, tx_request_byte_p_i,
Arguments_For_Both_Bytes_Counters: process (s_id_dat_frame_ok, s_consuming, tx_byte_request_p_i,
s_producing, rx_byte_ready_p_i, s_rx_bytes_c, s_prod_bytes_c)
begin
......@@ -656,7 +679,7 @@ begin
s_rx_byte_index <= (others => '0');
s_rst_prod_bytes_counter <= '0';
s_inc_prod_bytes_counter <= tx_request_byte_p_i;
s_inc_prod_bytes_counter <= tx_byte_request_p_i;
s_tx_byte_index <= std_logic_vector (s_prod_bytes_c);
......@@ -833,31 +856,31 @@ begin
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief: Essential buffering of the signals tx_last_byte_p_o, tx_byte_ready_p_o,tx_start_prod_p_o
--!@brief: Essential buffering of the signals tx_last_byte_p_o, tx_byte_request_accept_p_o,tx_start_prod_p_o
process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_last_byte_p_o <= '0';
s_tx_last_byte_p_d <= '0';
s_tx_byte_ready_p_d1 <= '0';
s_tx_byte_ready_p_d2 <= '0';
s_tx_start_prod_p <= '0';
tx_last_byte_p_o <= '0';
s_tx_last_byte_p_d <= '0';
s_tx_byte_request_accept_p_d1 <= '0';
s_tx_byte_request_accept_p_d2 <= '0';
s_tx_start_prod_p <= '0';
else
s_tx_last_byte_p_d <= s_tx_last_byte_p;
tx_last_byte_p_o <= s_tx_last_byte_p_d;
s_tx_byte_ready_p_d1 <= s_tx_byte_ready_p;
s_tx_byte_ready_p_d2 <= s_tx_byte_ready_p_d1;
s_tx_start_prod_p <= (s_prod_wait_turnar_time and s_time_c_is_zero);
s_tx_last_byte_p_d <= s_tx_last_byte_p;
tx_last_byte_p_o <= s_tx_last_byte_p_d;
s_tx_byte_request_accept_p_d1 <= s_tx_byte_request_accept_p;
s_tx_byte_request_accept_p_d2 <= s_tx_byte_request_accept_p_d1;
s_tx_start_prod_p <= (s_prod_wait_turnar_time and s_time_c_is_zero);
end if;
end if;
end process;
s_tx_byte_ready_p <= s_producing and (tx_request_byte_p_i or s_tx_start_prod_p);
s_tx_byte_request_accept_p <= s_producing and (tx_byte_request_p_i or s_tx_start_prod_p);
s_tx_last_byte_p <= s_producing and s_prod_data_length_match and tx_request_byte_p_i;
s_tx_last_byte_p <= s_producing and s_prod_data_length_match and tx_byte_request_p_i;
---------------------------------------------------------------------------------------------------
......@@ -869,8 +892,8 @@ begin
-- number of bytes of the Control & Data fields of a produced RP_DAT frame
prod_data_length_o <= s_prod_data_length;
--
tx_byte_ready_p_o <= s_tx_byte_ready_p_d2;
-- response to WF_tx_serializer request for a byte
tx_byte_request_accept_p_o <= s_tx_byte_request_accept_p_d2;
-- Index of the byte being consumed or produced
prod_cons_byte_index_o <= s_tx_byte_index when s_producing = '1' else s_rx_byte_index;
......
wf_inputs_synchronizer.vhd
View file @ 15122c97
......@@ -27,10 +27,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit synchronises all the input signals with to the uclk or wb_clk, to be used
-- by all the other units of nanoFIP; a set of 3ple buffers is used for each signal.
-- Note: Because of the 3ple buffering, transitions on input signals of less than 2
-- clk cycles are not considered.
--! @brief The unit synchronises all the input signals with to the uclk or wb_clk, to be used
-- by all the other units of nanoFIP; a set of 3ple buffers is used for each signal.
-- Note: Because of the 3ple buffering, transitions on input signals of less than 2
-- clk cycles are not considered.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -45,12 +45,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -99,16 +99,15 @@ entity WF_inputs_synchronizer is
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
dat_a_i : in std_logic_vector(15 downto 0);
wb_adr_a_i : in std_logic_vector(9 downto 0);
wb_cyc_a_i : in std_logic;
wb_rst_a_i : in std_logic; --! WISHBONE reset
wb_stb_a_i : in std_logic;
wb_we_a_i : in std_logic;
-- nanoFIP User Interface, non WISHBONE
-- nanoFIP User Interface, NON WISHBONE
dat_a_i : in std_logic_vector(15 downto 0);
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
......@@ -125,7 +124,6 @@ entity WF_inputs_synchronizer is
nostat_o : out std_logic;
rstin_o : out std_logic;
slone_o : out std_logic;
rstin_f_edge_o : out std_logic;
-- nanoFIP WorldFIP Settings
c_id_o : out std_logic_vector(3 downto 0);
......@@ -135,15 +133,13 @@ entity WF_inputs_synchronizer is
subs_o : out std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
wb_adri_o : out std_logic_vector(9 downto 0);
wb_cyc_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_we_o : out std_logic;
-- nanoFIP User Interface, non WISHBONE
-- nanoFIP User Interface, NON WISHBONE
slone_dati_o : out std_logic_vector(15 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
......@@ -173,12 +169,10 @@ architecture rtl of WF_inputs_synchronizer is
signal s_mid_d1, s_mid_d2, s_mid_d3, s_cid_d1, s_cid_d2, s_cid_d3 : std_logic_vector(3 downto 0);
signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3, s_fd_rxcdn_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3 : std_logic_vector(2 downto 0);
signal s_u_rst_d3 : std_logic_vector(3 downto 0);
signal s_u_rst_d3 : std_logic_vector(2 downto 0);
signal s_nostat_d3, s_slone_d3 : std_logic_vector(2 downto 0);
signal s_wb_adr_d1, s_wb_adr_d2, s_wb_adr_d3 : std_logic_vector(9 downto 0);
signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0);
signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0);
signal s_wb_dati_d1, s_wb_dati_d2, s_wb_dati_d3 : std_logic_vector(7 downto 0);
signal s_slone_dati_d1, s_slone_dati_d3, s_slone_dati_d2 :std_logic_vector(15 downto 0);
......@@ -192,12 +186,11 @@ begin
RSTIN_synchronisation_with_uclk: process (uclk_i)
begin
if rising_edge (uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (2 downto 0) & rstin_a_i;
s_u_rst_d3 <= s_u_rst_d3 (1 downto 0) & rstin_a_i;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rstin_o <= s_u_rst_d3(2);
rstin_f_edge_o <= s_u_rst_d3(3) and (not s_u_rst_d3(2));
---------------------------------------------------------------------------------------------------
......@@ -293,12 +286,6 @@ begin
begin
if rising_edge (wb_clk_i) then
if wb_rst_a_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_dati_d1 <= (others => '0');
s_wb_dati_d2 <= (others => '0');
s_wb_dati_d3 <= (others => '0');
s_wb_adr_d1 <= (others => '0');
s_wb_adr_d2 <= (others => '0');
s_wb_adr_d3 <= (others => '0');
s_wb_stb_d1 <= '0';
s_wb_stb_d2 <= '0';
s_wb_stb_d3 <= '0';
......@@ -310,14 +297,6 @@ begin
s_wb_cyc_d3 <= '0';
else
s_wb_dati_d3 <= s_wb_dati_d2;
s_wb_dati_d2 <= s_wb_dati_d1;
s_wb_dati_d1 <= dat_a_i (7 downto 0);
s_wb_adr_d3 <= s_wb_adr_d2;
s_wb_adr_d2 <= s_wb_adr_d1;
s_wb_adr_d1 <= wb_adr_a_i;
s_wb_stb_d1 <= wb_stb_a_i;
s_wb_stb_d2 <= s_wb_stb_d1;
s_wb_stb_d3 <= s_wb_stb_d2;
......@@ -335,8 +314,6 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- --
wb_dati_o <= s_wb_dati_d3;
wb_adri_o <= s_wb_adr_d3;
wb_cyc_o <= s_wb_cyc_d3;
wb_we_o <= s_wb_we_d3;
wb_stb_o <= s_wb_stb_d3;
......
wf_manch_code_viol_check.vhd
View file @ 15122c97
......@@ -62,12 +62,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx_deglitcher \n
--! WF_reset_unit \n
--! WF_rx_deglitcher \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_manch_encoder.vhd
View file @ 15122c97
......@@ -47,7 +47,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! \n<b>Modified by:</b> \n
--! Evangelia Gousiou \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_model_constr_decoder.vhd
View file @ 15122c97
......@@ -52,12 +52,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit\n
--! WF_reset_unit\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_package.vhd
View file @ 15122c97
......@@ -41,7 +41,7 @@ use ieee.numeric_std.all;
--
--
--! \n<b>Modified by:</b> \n
--! Evangelia Gousiou \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -86,8 +86,9 @@ package WF_package is
"0001110001101011";
---------------------------------------------------------------------------------------------------
-- Constants regarding the Manchester 2 coding --
-- Constants regarding the the ID_DAT and RP_DAT frame structure --
---------------------------------------------------------------------------------------------------
constant VP : std_logic_vector (1 downto 0) := "11";
......@@ -95,15 +96,11 @@ package WF_package is
constant ONE : std_logic_vector (1 downto 0) := "10";
constant ZERO : std_logic_vector (1 downto 0) := "01";
constant c_PRE : std_logic_vector (15 downto 0) := ONE & ZERO & ONE & ZERO & ONE & ZERO & ONE & ZERO;
constant c_FSD : std_logic_vector (15 downto 0) := ONE & VP & VN & ONE & ZERO & VN & VP & ZERO;
constant c_FES : std_logic_vector (15 downto 0) := ONE & VP & VN & VP & VN & ONE & ZERO & ONE;
constant c_FSS : std_logic_vector (31 downto 0) := c_PRE & c_FSD;
---------------------------------------------------------------------------------------------------
-- Constants regarding the the ID_DAT and RP_DAT frame structure --
---------------------------------------------------------------------------------------------------
constant PRE : std_logic_vector (15 downto 0) := ONE & ZERO & ONE & ZERO & ONE & ZERO & ONE & ZERO;
constant FSD : std_logic_vector (15 downto 0) := ONE & VP & VN & ONE & ZERO & VN & VP & ZERO;
constant FES : std_logic_vector (15 downto 0) := ONE & VP & VN & VP & VN & ONE & ZERO & ONE;
constant FSS : std_logic_vector (31 downto 0) := PRE & FSD;
---------------------------------------------------------------------------------------------------
......@@ -222,7 +219,7 @@ package WF_package is
(c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD),
silence => integer (5160000.0 / c_QUARTZ_PERIOD)),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
silence => integer (150000.0 / c_QUARTZ_PERIOD)),
c_2M5_INDEX => (turnaround => integer (6000.0 / c_QUARTZ_PERIOD),
......@@ -236,7 +233,7 @@ package WF_package is
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the consumed & produced variables --
---------------------------------------------------------------------------------------------------
-- Construction of a table that gathers main information for all the variables
-- Construction of a table that groups main information for all the variables
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_whatever);
......@@ -362,7 +359,6 @@ package WF_package is
wb_cyc_a_i : in std_logic;
wb_we_a_i : in std_logic;
wb_stb_a_i : in std_logic;
wb_adr_a_i : in std_logic_vector(9 downto 0);
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
......@@ -374,7 +370,6 @@ package WF_package is
p3_lgth_a_i : in std_logic_vector(2 downto 0);
-----------------------------------------------------------------
rstin_o : out std_logic;
rstin_f_edge_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
fd_wdgn_o : out std_logic;
......@@ -387,8 +382,6 @@ package WF_package is
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_adri_o : out std_logic_vector(9 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
......@@ -433,17 +426,17 @@ end component WF_inputs_synchronizer;
component WF_tx_serializer
generic (c_TX_CLK_BUFF_LGTH : natural);
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
start_prod_p_i : in std_logic;
byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
start_prod_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
-------------------------------------------------------------------------
request_byte_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic
byte_request_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic
-------------------------------------------------------------------------
);
end component WF_tx_serializer;
......@@ -478,16 +471,13 @@ end component WF_inputs_synchronizer;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
cons_ctrl_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_lgth_byte_o : out std_logic_vector (7 downto 0);
......@@ -524,9 +514,7 @@ end component WF_inputs_synchronizer;
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector(9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
wb_adr_i : in std_logic_vector(8 downto 0);
var_i : in t_var;
byte_index_i : in std_logic_vector (7 downto 0);
rst_rx_unit_p_i : in std_logic;
......@@ -538,7 +526,6 @@ end component WF_inputs_synchronizer;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
byte_ready_p_o : out std_logic;
fss_received_p_o : out std_logic;
......@@ -562,10 +549,8 @@ end component WF_inputs_synchronizer;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_adr_i : in std_logic_vector(8 downto 0);
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector(15 downto 0);
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
......@@ -576,7 +561,7 @@ end component WF_inputs_synchronizer;
data_length_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
start_prod_p_i : in std_logic;
byte_ready_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
......@@ -586,15 +571,14 @@ end component WF_inputs_synchronizer;
model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0);
--------------------------------------------------------------------------
request_byte_p_o : out std_logic;
byte_request_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
var3_rdy_o : out std_logic;
wb_ack_prod_p_o : out std_logic
var3_rdy_o : out std_logic
--------------------------------------------------------------------------
);
end component WF_production;
......@@ -611,22 +595,19 @@ end component WF_production;
constr_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector (7 downto 0);
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
nFIP_status_byte_i : in std_logic_vector (7 downto 0);
mps_status_byte_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
data_length_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
byte_ready_p_i : in std_logic;
byte_being_sent_p_i : in std_logic;
var3_rdy_i : in std_logic;
---------------------------------------------------------------
rst_status_bytes_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
wb_ack_prod_p_o : out std_logic
byte_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
end component WF_prod_bytes_retriever;
......@@ -658,14 +639,14 @@ end component WF_production;
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
tx_request_byte_p_i : in std_logic;
tx_byte_request_p_i : in std_logic;
rx_fss_received_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
---------------------------------------------------------------
tx_byte_ready_p_o : out std_logic;
tx_byte_request_accept_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;
tx_start_prod_p_o : out std_logic;
prod_cons_byte_index_o : out std_logic_vector (7 downto 0);
......@@ -682,8 +663,7 @@ end component WF_production;
port (
uclk_i : in std_logic;
rstin_i : in std_logic;
rstin_f_edge_i : in std_logic;
rstpon_i : in std_logic;
rstpon_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
var_i : in t_var;
rst_nFIP_and_FD_p_i : in std_logic;
......@@ -978,18 +958,41 @@ end component WF_production;
);
end component WF_cons_outcome;
---------------------------------------------------------------------------------------------------
component WF_prod_permit is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
var_i : in t_var;
var3_rdy_o : out std_logic
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
var_i : in t_var;
---------------------------------------------------------------
var3_rdy_o : out std_logic
---------------------------------------------------------------
);
end component WF_prod_permit;
---------------------------------------------------------------------------------------------------
component WF_wb_controller is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_r_edge_p_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_id_i : in std_logic_vector (2 downto 0);
---------------------------------------------------------------
wb_ack_prod_p_o : out std_logic;
wb_ack_p_o : out std_logic
---------------------------------------------------------------
);
end component WF_wb_controller;
---------------------------------------------------------------------------------------------------
end WF_package;
......
wf_prod_bytes_retriever.vhd
View file @ 15122c97
......@@ -29,7 +29,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @brief After an ID_DAT frame requesting for a variable to be produced, the unit provides
--! to the WF_tx_serializer unit one by one, \n all the bytes of data needed for the
--! RP_DAT frame (apart from the FSS, FCS and FES bytes).
--! RP_DAT frame (apart from the FSS, FCS and FES bytes). The coordination of the
--! retreival is done through the WF_engine_control and the signal byte_index_i.
--!
--! General structure of a produced RP_DAT frame :
--! ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
......@@ -55,10 +56,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
--! o var_3 : if the operation is in stand-alone mode, the unit retreives the
--! user-data bytes from the "nanoFIP User Interface, NON_WISHBONE"
--! bus DAT_I. If the operation is in memory mode, it retreives them
--! from the Produced RAM. The unit retreives the MPS and nanoFIP
--! status bytes from the WF_status_bytes_gen, and the LGTH byte
--! from the WF_prod_data_lgth_calc (in the WF_engine_control). The
--! bus DAT_I.
--! If the operation is in memory mode, it retreives them from the
--! Produced RAM.
--! The unit retreives the MPS and nanoFIP status bytes from the
--! WF_status_bytes_gen, and the LGTH byte from the
--! WF_prod_data_lgth_calc (in the WF_engine_control). The
--! rest of the bytes (Ctrl & PDU) come from the WF_package.
--! ______ _______ ______ ________________________________________ _______ _______
--! |_Ctrl_||__PDU__|_LGTH_|_____________..User-Data..______________|_nstat_|__MPS__||
......@@ -77,12 +80,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_prod_permit \n
--! WF_status_bytes_gen \n
--! WF_model_constr_dec \n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_prod_permit \n
--! WF_status_bytes_gen \n
--! WF_model_constr_dec \n
--
---------------------------------------------------------------------------------------------------
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
......@@ -97,7 +101,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_engine_control and the configuration of the memory needed changes)
--! -> 11/2010 v0.04 EG for simplification, new unit Slone_Data_Sampler created
--! -> 4/1/2011 v0.05 EG unit renamed from WF_prod_bytes_to_tx to WF_prod_bytes_retriever;
--! input byte_ready_p_i added, so that the reseting of status bytes
--! input byte_being_sent_p_i added, so that the reseting of status bytes
--! does not pass from the engine; clening-up+commenting
--
--
......@@ -126,70 +130,65 @@ entity WF_prod_bytes_retriever is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
uclk_i : in std_logic; --! 40MHz clock
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector(9 downto 0); --! WISHBONE address to memory
wb_data_i : in std_logic_vector(7 downto 0); --! WISHBONE data bus
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_stb_r_edge_p_i : in std_logic; --! rising edge of WISHBONE strobe
wb_we_i : in std_logic; --! WISHBONE write enable
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector(8 downto 0); --! WISHBONE address to memory
wb_data_i : in std_logic_vector(7 downto 0); --! WISHBONE data bus
-- Signal from the WF_wb_controller
wb_ack_prod_p_i : in std_logic; --! WISHBONE acknowledge
-- latching moment of wb_data_i
-- nanoFIP User Interface, NON WISHBONE (synchronized with uclk)
slone_data_i : in std_logic_vector(15 downto 0);--! input data bus for slone mode
slone_data_i : in std_logic_vector(15 downto 0); --! input data bus for slone mode
-- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector(7 downto 0); --! pointer to frame bytes
-- (RP_DAT.Control & RP_DAT.Data bytes)
byte_ready_p_i : in std_logic; --! indication that a byte is ready
--! to be delivered
data_length_i : in std_logic_vector(7 downto 0); --!# bytes of the Conrol&Data fields
-- of the RP_DAT frame; includes:
-- 1 byte RP_DAT.Control,
-- 1 byte RP_DAT.Data.PDU_type,
-- 1 byte RP_DAT.Data.LENGTH
-- 0-124 bytes of RP_DAT.Data,
-- 1 byte RP_DAT.Data.MPS_status &
-- optionally 1 byte for the
-- RP_DAT.Data.nanoFIP_status
byte_index_i : in std_logic_vector(7 downto 0); --!index of the byte to be retrieved
byte_being_sent_p_i : in std_logic; --! indication that a byte is ready
--! to be delivered
data_length_i : in std_logic_vector(7 downto 0); --! # bytes of the Conrol&Data fields
-- of the RP_DAT frame; includes:
-- 1 byte RP_DAT.Control,
-- 1 byte RP_DAT.Data.PDU_type,
-- 1 byte RP_DAT.Data.LENGTH
-- 0-124 bytes of RP_DAT.Data,
-- 1 byte RP_DAT.Data.MPS_status &
-- optionally 1 byte for the
-- RP_DAT.Data.nanoFIP_status
var_i : in t_var; --! variable type that is being treated
var_i : in t_var; --!variable type that is being treated
-- Signals from the WF_prod_permit
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- Signals from the WF_status_bytes_gen
mps_status_byte_i : in std_logic_vector(7 downto 0); --! MPS status byte
nFIP_status_byte_i : in std_logic_vector(7 downto 0); --! nanoFIP status byte
mps_status_byte_i : in std_logic_vector(7 downto 0); --! MPS status byte
nFIP_status_byte_i : in std_logic_vector(7 downto 0); --! nanoFIP status byte
-- Signals from the WF_model_constr_dec unit
constr_id_dec_i : in std_logic_vector(7 downto 0);--! decoded constructor id settings
model_id_dec_i : in std_logic_vector(7 downto 0);--! decoded model id settings
constr_id_dec_i : in std_logic_vector(7 downto 0); --! decoded constructor id settings
model_id_dec_i : in std_logic_vector(7 downto 0); --! decoded model id settings
-- OUTPUTS
-- Signal to the WF_status_bytes_gen
rst_status_bytes_p_o : out std_logic; --! reset for the nanoFIP&MPS status
--! status bytes. It is activated after
--! the delivery of the last one (MPS)
rst_status_bytes_p_o : out std_logic; --! reset for the nanoFIP&MPS status
--! status bytes.It is activated after
--! the delivery of the last one (MPS)
-- Signal to the WF_tx_serializer
byte_o : out std_logic_vector(7 downto 0);--! output byte to be serialized
byte_o : out std_logic_vector(7 downto 0) --! output byte to be serialized
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_prod_p_o : out std_logic --! WISHBONE acknowledge
-- response to master's strobe
);
end entity WF_prod_bytes_retriever;
......@@ -199,10 +198,8 @@ end entity WF_prod_bytes_retriever;
--=================================================================================================
architecture rtl of WF_prod_bytes_retriever is
signal s_wb_ack_prod_p : std_logic;
signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0);
signal s_byte_index_aux : integer range 0 to 15;
signal s_mem_wr_en_B_d3 : std_logic_vector (2 downto 0);
signal s_lgth_byte, s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0);
signal s_byte_index : std_logic_vector (7 downto 0);
signal s_mem_addr_A : std_logic_vector (8 downto 0);
......@@ -236,37 +233,9 @@ begin
clk_portb_i => wb_clk_i, -- WISHBONE clock
addr_portb_i => wb_adr_i (8 downto 0),-- address of byte to be written
data_portb_i => wb_data_i, -- byte to be written
write_en_portb_i => s_mem_wr_en_B_d3(2)); -- WISHBONE write enable
write_en_portb_i => wb_ack_prod_p_i); -- WISHBONE write enable
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Delay_mem_wr_en: since the input buses wb_data_i and wb_addr_i are
--! the triply buffered versions of the DAT_I and ADR_I, the signal write_en_portb_i has to be delayed
--! too. As write_en_portb_i we use the wb_ack_prod_p signal.
Delay_mem_wr_en: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
s_mem_wr_en_B_d3 <= s_mem_wr_en_B_d3(1 downto 0) & s_wb_ack_prod_p ;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Generate_wb_ack_prod_p_o: Generation of the wb_ack_prod_p_o signal
--! (acknowledgement from WISHBONE Slave of the write cycle, as a response to the master's storbe).
--! wb_ack_prod_p_o is 1 wclk-wide pulse if the wb_cyc and wb_we are asserted and the WISHBONE
--! input address corresponds to an address in the Produced memory block.
Generate_wb_ack_prod_p_o: s_wb_ack_prod_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 7) = "010") and
(wb_we_i = '1') and
(wb_cyc_i = '1'))
else '0';
wb_ack_prod_p_o <= s_wb_ack_prod_p;
---------------------------------------------------------------------------------------------------
-- Produced bytes from DAT_I --
......@@ -300,9 +269,10 @@ begin
--! WF_status_bytes_gen or the WF_model_constr_decoder units.\n The output byte "byte_o" is sent to
--! the WF_tx_serializer unit for manchester encoding and serialization.
Bytes_Generation: process (var_i, s_byte_index, data_length_i, constr_id_dec_i, model_id_dec_i,
Bytes_Generation: process (var_i, s_byte_index, data_length_i, constr_id_dec_i, model_id_dec_i,
nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_byte_index_aux,
s_mem_byte, slone_i, s_byte_index_aux, nostat_i, byte_ready_p_i, s_lgth_byte)
s_mem_byte, s_byte_index_aux, nostat_i, byte_being_sent_p_i,
s_lgth_byte, slone_i)
begin
......@@ -386,10 +356,10 @@ begin
-- The last byte is the MPS status
elsif s_byte_index = (data_length_i) then
byte_o <= mps_status_byte_i;
rst_status_bytes_p_o <= byte_ready_p_i; -- reset signal for both status bytes. The reset
-- arrives after having sent the MPS byte to the
-- WF_tx_serializer for it to be delivered.
rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes.
-- The reset arrives after having sent
-- the MPS byte to the WF_tx_serializer
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The rest of the bytes come from the memory
else
......@@ -431,13 +401,12 @@ begin
-- The last byte is the MPS status
elsif s_byte_index = data_length_i then
byte_o <= mps_status_byte_i;
rst_status_bytes_p_o <= byte_ready_p_i; -- reset signal for both status bytes. The reset
-- arrives after having sent the MPS byte to the
-- WF_tx_serializer for it to be delivered.
rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes.
-- The reset arrives after having sent the
-- MPS byte to the WF_tx_serializer
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The rest of the bytes come from the input bus data_i(15:0)
else
byte_o <= s_slone_byte;
rst_status_bytes_p_o <= '0';
......
wf_prod_bytes_to_dati.vhd
View file @ 15122c97
......@@ -45,12 +45,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_reset_unit \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_prod_data_lgth_calc.vhd
View file @ 15122c97
......@@ -57,11 +57,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_prod_permit.vhd
View file @ 15122c97
......@@ -44,12 +44,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_production.vhd
View file @ 15122c97
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_production.vhd
--! @file WF_production.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -27,42 +27,53 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit gathers the main actions that regard data production.
--! @brief The unit groups the main actions that regard data production.
--! It instantiates the units:
--!
--! o WF_tx_serializerr : that receives bytes from the WF_prod_bytes_retriever,
--! encodes them (Manchester 2), adds the FSS, FCS & FES
--! fields and puts one by one the encoded bits to the
--! FIELDRIVE output FD_TXD.
--! o WF_prod_bytes_retriever : that retreives user-data bytes from the Produced RAM
--! or the "nanoFIP User Interface, NON-WISHBONE" data bus
--! DAT_I, and other bytes(PDU,LGTH,Ctrl,MPS,nFIP status)
--! from the WF_package, WF_status_bytes_gen,
--! WF_prod_data_lgth_calc units.
--! o WF_status_bytes_gen : that receives information from the WF_consumption
--! o WF_tx_serializer : that receives bytes from the WF_prod_bytes_retriever,
--! encodes them (Manchester 2), adds the FSS, FCS & FES
--! fields and puts one by one bits to the FIELDRIVE output
--! FD_TXD. Also handles the nanoFIP output FD_TXENA.
--!
--! o WF_prod_bytes_retriever: that retrieves
--! user-data bytes: from the Produced RAM or the
--! "nanoFIP User Interface, NON-WISHBONE" data bus DAT_I,
--! PDU,Ctrl bytes : from the WF_package
--! MPS,nFIP status: from the WF_status_bytes_gen
--! LGTH byte : from the WF_prod_data_lgth_calc
--! and following the external signals of the
--! WF_engine_control forwards them to the WF_tx_serializer.
--!
--! o WF_status_bytes_gen : that receives information from the WF_consumption unit,
--! the FIELDRIVE and "User Interface,NON-WISHBONE" inputs
--! and outputs, to form the nanoFIP & MPS status bytes
--!
--! o WF_prod_permit : that handles the"nanoFIP User Interface, NON-WISHBONE"
--! signal VAR3_RDY
--! o WF_prod_permit : that signals the user that a variable can safely be
--! written (through the "nanoFIP User Interface,
--! NON-WISHBONE" signal VAR3_RDY)
--!
--! __ _________________________________
--! | | |
--! Level 2 | WF_prod_permit |
--! |__ |_________________________________|
--! _________________________________
--! | |
--! | WF_prod_permit |
--! |_________________________________|
--! ^
--! _________________________________ ________________
--! | | | |
--! | WF_prod_bytes_retriever | < | WF_status_bytes|
--! | | | _gen |
--! |_________________________________| |________________|
--! ^
--! __ _________________________________ ________________
--! | | | | |
--! Level 1 | WF_prod_bytes_retriever | < | WF_status_bytes|
--! | | | | _gen |
--! |__ |_________________________________| |________________|
--! _________________________________
--! | |
--! | WF_tx_serializerr |
--! |_________________________________|
--! ^
--! __ _________________________________
--! | | |
--! Level 0 | WF_tx_serializerr |
--! |__ |_________________________________|
--!
--! _______________________________________________________________
--! 0__________________________FIELDBUS____________________________O
--!
--! Note: In the entity declaration of this unit, below each input signal, we mark
--! which of the instantiated units needs it.
--!
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
......@@ -77,20 +88,21 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_prod_bytes_retriever \n
--! WF_status_bytes_gen \n
--! WF_tx_serializer \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_consumption \n
--! WF_engine_control \n
--! WF_tx_rx_osc \n
--! WF_model_constr_decoder \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! ->
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo
......@@ -118,103 +130,113 @@ entity WF_production is
uclk_i : in std_logic;
--! WF_prod_bytes_retriever : for the selection of data bytes from the RAM or the DATI bus
--! WF_status_bytes_gen : the MPS status byte is different according to the operational mode
slone_i : in std_logic;
--! WF_prod_bytes_retriever : for the delivery or not of the nanoFIP status byte
-- WF_prod_bytes_retriever : for the selection of data bytes from the RAM or the DATI bus
-- WF_status_bytes_gen : the MPS status byte is different according to the operational mode
nostat_i : in std_logic;
-- WF_prod_bytes_retriever : for the delivery or not of the nanoFIP status byte
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit unit
nfip_rst_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
-- nanoFIP User Interface, WISHBONE Slave
--! WF_prod_bytes_retriever : for the managment of the Production RAM
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector(9 downto 0);
wb_adr_i : in std_logic_vector(8 downto 0);
wb_data_i : in std_logic_vector(7 downto 0);
wb_cyc_i : in std_logic;
wb_stb_r_edge_p_i : in std_logic;
wb_we_i : in std_logic;
-- WF_prod_bytes_retriever : for the managment of the Production RAM
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_wb_controller
wb_ack_prod_p_i : in std_logic;
-- WF_prod_bytes_retriever : for the latching of wb_data_i
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, NON-WISHBONE (synchronized with uclk)
--! WF_prod_bytes_retriever : for the bytes retreival in stand-alone mode
slone_data_i : in std_logic_vector(15 downto 0);
-- WF_prod_bytes_retriever : for the bytes retreival in stand-alone mode
--! WF_status_bytes_gen : for the nanoFIP status byte, bits 2, 3
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
-- WF_status_bytes_gen : for the nanoFIP status byte, bits 2, 3
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP FIELDRIVE (synchronized with uclk)
--! WF_status_bytes_gen : for the nanoFIP status byte, bits 6, 7
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
-- WF_status_bytes_gen : for the nanoFIP status byte, bits 6, 7
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_engine_control
--! WF_prod_bytes_retriever : for the definition of the bytes to be delivered
byte_index_i : in std_logic_vector (7 downto 0);
data_length_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
var_i : in t_var;-- also for the WF_prod_permit for the VAR3_RDY generation
-- WF_prod_bytes_retriever : for the definition of the bytes to be delivered
--! WF_tx_serializer : for the delivery coordination
byte_ready_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
start_prod_p_i : in std_logic;
-- WF_tx_serializer : for the delivery coordination
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_consumption
--! WF_status_bytes_gen : for the generation of the nanoFIP status byte, bits 2, 4, 5
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
-- WF_status_bytes_gen : for the generation of the nanoFIP status byte, bits 2, 4, 5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_rx_tx_osc
-- WF_tx_serializer : for the transmission synchronization
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
-- WF_tx_serializer : for the transmission synchronization
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_model_constr_decoder unit
--! WF_prod_bytes_retriever : for the production of a var_identif
constr_id_dec_i : in std_logic_vector (7 downto 0);
model_id_dec_i : in std_logic_vector (7 downto 0);
-- WF_prod_bytes_retriever : for the production of a var_identif
-------------------------------------------------------------------------------------------------
-- OUTPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the WF_engine_control
request_byte_p_o : out std_logic;
byte_request_p_o : out std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; --! transmitter data
tx_enable_o : out std_logic; --! transmitter enable
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, NON-WISHBONE outputs
u_cacer_o : out std_logic; --! nanoFIP status byte, bit 2
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
u_pacer_o : out std_logic; --! nanoFIP status byte, bit 3
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
var3_rdy_o : out std_logic; --! signals the user that data can safely be written
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk) output
wb_ack_prod_p_o : out std_logic --! WISHBONE acknowledge
var3_rdy_o : out std_logic --! signals the user that data can safely be written
);
end entity WF_production;
......@@ -238,7 +260,9 @@ begin
---------------------------------------------------------------------------------------------------
-- Production Level 3 : VAR3_RDY generator --
---------------------------------------------------------------------------------------------------
VAR3_RDY_generation: WF_prod_permit
--! @brief Instantiation of the WF_prod_permit unit
production_VAR3_RDY_generation: WF_prod_permit
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......@@ -255,7 +279,7 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_prod_bytes_retriever unit
production_level_1 : WF_prod_bytes_retriever
production_bytes_retriever : WF_prod_bytes_retriever
port map(
uclk_i => uclk_i,
model_id_dec_i => model_id_dec_i,
......@@ -265,22 +289,19 @@ begin
nfip_rst_i => nfip_rst_i,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
wb_stb_r_edge_p_i => wb_stb_r_edge_p_i,
wb_cyc_i => wb_cyc_i,
wb_we_i => wb_we_i,
wb_ack_prod_p_i => wb_ack_prod_p_i,
nFIP_status_byte_i => s_stat,
mps_status_byte_i => s_mps,
var_i => var_i,
byte_index_i => byte_index_i,
byte_ready_p_i => byte_ready_p_i,
byte_being_sent_p_i => byte_request_accept_p_i,
data_length_i => data_length_i,
wb_data_i => wb_data_i,
slone_data_i => slone_data_i,
var3_rdy_i => s_var3_rdy,
-----------------------------------------------
rst_status_bytes_p_o => s_rst_status_bytes_p,
byte_o => s_byte_to_tx,
wb_ack_prod_p_o => wb_ack_prod_p_o
byte_o => s_byte_to_tx
-----------------------------------------------
);
......@@ -291,7 +312,7 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_status_bytes_gen unit
status_bytes_gen : WF_status_bytes_gen
production_status_bytes_generator : WF_status_bytes_gen
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......@@ -324,23 +345,24 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_tx_serializer unit
production_level_0: WF_tx_serializer
production_serializer: WF_tx_serializer
generic map(c_TX_CLK_BUFF_LGTH => c_TX_CLK_BUFF_LGTH)
PORT MAP(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_prod_p_i => start_prod_p_i,
byte_ready_p_i => byte_ready_p_i,
byte_i => s_byte_to_tx,
last_byte_p_i => last_byte_p_i,
tx_clk_p_buff_i => tx_clk_p_buff_i,
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_prod_p_i => start_prod_p_i,
byte_request_accept_p_i => byte_request_accept_p_i,
byte_i => s_byte_to_tx,
last_byte_p_i => last_byte_p_i,
tx_clk_p_buff_i => tx_clk_p_buff_i,
-----------------------------------------------
tx_data_o => tx_data_o,
request_byte_p_o => request_byte_p_o,
tx_enable_o => tx_enable_o
tx_data_o => tx_data_o,
byte_request_p_o => byte_request_p_o,
tx_enable_o => tx_enable_o
-----------------------------------------------
);
var3_rdy_o <= s_var3_rdy;
......
wf_reset_unit.vhd
View file @ 15122c97
......@@ -146,7 +146,6 @@ entity WF_reset_unit is
uclk_i : in std_logic; --! 40 MHz clock
rstin_i : in std_logic; --! initialisation control, active low
rstpon_i : in std_logic; --! Power On Reset, active low
rstin_f_edge_i : in std_logic; --! rising edge on RSTIN
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_engine_control unit
......@@ -252,16 +251,15 @@ begin
--!@brief Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st,rstin_f_edge_i,
s_counter_is_ten,rstin_i,s_counter_is_four,
s_counter_is_full)
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, rstin_i, s_counter_is_four,
s_counter_is_ten, s_counter_is_full)
begin
case rstin_st is
when idle =>
if rstin_i = '0' then -- RSTIN active
if rstin_i = '0' then -- RSTIN active
nx_rstin_st <= rstin_eval;
else
......@@ -269,7 +267,7 @@ begin
end if;
when rstin_eval =>
if rstin_i = '1' then -- RSTIN deactivated before the 8 cycles
if rstin_i = '1' then -- RSTIN deactivated
nx_rstin_st <= idle;
else
......@@ -606,19 +604,16 @@ free_counter: WF_incr_counter
---------------------------------------------------------------------------------------------------
nFIP_rst_o <= s_intern_rst_from_RSTIN or s_intern_rst_from_var_rst or s_por; -- nanoFIP internal
-- reset; resets
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_por);
-- reset; resets all
-- logic apart from
-- WISHBONE
Outputs_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (s_por = '1') or (s_intern_rst_from_RSTIN = '1') or (s_intern_rst_from_var_rst = '1') then
rston_o <= '1'; -- active low
else
rston_o <= not s_rston;
rston_o <= not s_rston;
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_por);
end if;
end if;
end process;
......
wf_rx_deglitcher.vhd
View file @ 15122c97
......@@ -47,7 +47,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
-- @date 23/08/2010
......@@ -59,13 +58,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_tx-_rx_osc \n
--! WF_reset_unit \n
--! WF_tx-_rx_osc \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_rx_deserializer.vhd
View file @ 15122c97
......@@ -98,12 +98,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! units WF_rx_manch_code_check and Incoming_Bits_Index created;
--! each manch bit of FES checked (bf was just each bit, so any D5 was FES)
--! code cleaned-up + commented.\n
--! -> 12/2010 v0.02 EG CRC_ok pulse transfered 16 bits later to match the FES;
--! -> 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES;
--! like this we confirm that the CRC_ok_p arrived just before the FES,
--! and any 2 bytes that could by chanche be seen as CRC, are neglected.
--! FSM data_field_byte state: redundant code removed:
--! "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle"
--! code(more!)cleaned-up
--! -> 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if
--! bytes with size different than 8 have preceeded.
--
---------------------------------------------------------------------------------------------------
--
......@@ -186,10 +188,10 @@ architecture rtl of WF_rx_deserializer is
fsd_field, switch_to_deglitched, data_fcs_fes_fields);
signal rx_st, nx_rx_st : rx_st_t;
signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok_p_d16 : std_logic;
signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok_p_d16 : std_logic;
signal s_fsd_last_bit, s_fes_wrong_bit, s_sample_manch_bit_p_d1 : std_logic;
signal s_fes_detected_p, s_fes_detection_window : std_logic;
signal s_manch_not_ok, s_switching_to_deglitched : std_logic;
signal s_fes_detected_p : std_logic;
signal s_manch_not_ok, s_switching_to_deglitched : std_logic;
signal s_receiving_fsd, s_receiving_bytes, s_receiving_pre : std_logic;
signal s_decr_manch_bit_index_p, s_manch_bit_index_load : std_logic;
signal s_manch_bit_index_is_zero, s_edge_outside_manch_window_p : std_logic;
......@@ -198,7 +200,7 @@ architecture rtl of WF_rx_deserializer is
signal s_manch_r_edge_p, s_manch_f_edge_p : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned(3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_CRC_ok_p_buff : std_logic_vector (14 downto 0);
signal s_CRC_ok_p_buff, s_arriving_fes : std_logic_vector (15 downto 0);
--=================================================================================================
......@@ -488,15 +490,15 @@ architecture rtl of WF_rx_deserializer is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FSD aux signals concurrent assignments:
s_fsd_bit <= s_receiving_fsd and FSD (to_integer(s_manch_bit_index));
s_fsd_bit <= s_receiving_fsd and c_FSD (to_integer(s_manch_bit_index));
s_fsd_last_bit <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor rxd_filtered_i) and sample_manch_bit_p_i;
-- FES aux signals concurrent assignments :
s_fes_bit <= s_receiving_bytes and FES (to_integer(s_manch_bit_index));
s_fes_bit <= s_receiving_bytes and c_FES (to_integer(s_manch_bit_index));
s_fes_wrong_bit <= (s_fes_bit xor rxd_filtered_i) and sample_manch_bit_p_i;
s_fes_detected_p <=s_fes_detection_window and sample_manch_bit_p_i and s_manch_bit_index_is_zero;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process that according to the state of the FSM sets values to the
......@@ -517,7 +519,7 @@ architecture rtl of WF_rx_deserializer is
s_decr_manch_bit_index_p <= '0';
elsif s_switching_to_deglitched = '1' then -- preparation for the FSD byte
s_manch_bit_index_top <= to_unsigned(FSD'left-1,s_manch_bit_index_top'length);
s_manch_bit_index_top <= to_unsigned(c_FSD'left-1,s_manch_bit_index_top'length);
-- FSD'left-1: bc the 1st bit of the FSD has been covered at the state PRE_field_f_edge
s_manch_bit_index_load <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_manch_bit_index_p <= '0';
......@@ -539,27 +541,26 @@ architecture rtl of WF_rx_deserializer is
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process FES_Detector: creation of a window that is activated at the
--! beginning of an incoming byte and stays active as long as 16 incoming manch. bits match the FES.
--!@brief Synchronous process FES_Detector: The s_arriving_fes register is storing the last 16
--! manch. encoded bits received and the s_fes_detected_p indicates weather they match the FES.
FES_Detector: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fes_detection_window <= '1';
s_arriving_fes <= (others =>'0');
else
if s_manch_bit_index_is_zero = '1' and sample_manch_bit_p_i = '1' then
s_fes_detection_window <= '1';
elsif s_fes_wrong_bit = '1' then
s_fes_detection_window <= '0';
if s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
s_arriving_fes <= s_arriving_fes (14 downto 0) & rxd_filtered_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_fes_detected_p <= '1' when s_arriving_fes = (c_FES) and sample_manch_bit_p_i = '1' else '0';
......@@ -597,7 +598,7 @@ architecture rtl of WF_rx_deserializer is
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that manages the s_manch_code_viol_p signal: If at any point after
--!@brief Synchronous process that handles the s_manch_code_viol_p signal: If at any point after
--! the FSS and before the FES a code violation appears, the signal s_manch_not_ok stays
--! asserted until the end of the corresponding frame.
......@@ -613,22 +614,21 @@ architecture rtl of WF_rx_deserializer is
s_manch_not_ok <= '0';
else
if s_manch_code_viol_p ='1' and s_fes_wrong_bit ='1' then
s_manch_not_ok <= '1'; -- if a code violation appears
-- that doesn't belong to the FES
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that manages the signal crc_ok_p: The crc_ok_p coming from the CRC
--! calculator unit is delayed for 16 manch. encoded bits. The matching of this delayed pulse with
--! the FES pulse (s_fes_detected_p), would confirm that the two last bytes received before the
--! FES were the correct CRC.
--!@brief Synchronous process that handles the CRC signal: The crc_ok_p coming from the CRC
--! calculator unit is delayed for 16 manch. encoded bits. The matching of this delayed pulse
--! with the end of frame pulse (s_fes_detected_p), would confirm that the two last bytes
--! received before the FES were the correct CRC.
CRC_OK_pulse_delay: process (uclk_i)
begin
......@@ -644,22 +644,19 @@ architecture rtl of WF_rx_deserializer is
s_CRC_ok_p_buff <= (others => '0');
else
if s_sample_manch_bit_p_d1 = '1' then -- a delay is added to s_CRC_ok_p with
-- each manch. bit arrival. In total 15
-- delays have to be added in order to
-- arrive to the FES.
s_CRC_ok_p_buff <= s_CRC_ok_p_buff(13 downto 0) & s_CRC_ok_p;
-- a delay is added to s_CRC_ok_p with
if s_sample_manch_bit_p_d1 = '1' then -- each manch. bit arrival. In total 15
-- delays have to be added in order to
-- arrive to the FES.
s_CRC_ok_p_buff <= s_CRC_ok_p_buff(14 downto 0) & s_CRC_ok_p;
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(14); -- pulse 1 half-bit-clock period long
-- -- -- -- -- -- -- -- -- -- --
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(15); -- pulse 1 half-bit-clock period long
......
wf_rx_tx_osc.vhd
View file @ 15122c97
......@@ -61,15 +61,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03
--
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_synchronizer \n
--! WF_rx_deserializer \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_synchronizer \n
--! WF_rx_deserializer\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_status_bytes_gen.vhd
View file @ 15122c97
......@@ -52,19 +52,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 10/01/2011
--! @date 10/01/2011
--
--
--! @version v0.03
--! @version v0.03
--
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_consumption \n
--! WF_bytes_retriever \n
--! WF_prod_permit \n
--! WF_reset_unit \n
--! WF_consumption \n
--! WF_bytes_retriever \n
--! WF_prod_permit \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......
wf_tx_serializer.vhd
View file @ 15122c97
---------------------------------------------------------------------------------------------------
--! @file WF_tx_serializer.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx_serializer --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: WF_tx_serializer
--
--
--! @brief Serializes the WorldFIP data.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 07/2010
--
--
--! @version v0.03
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine \n
--! tx_engine \n
--! clk_gen \n
--! WF_reset_unit \n
--! consumed_ram \n
--
--
--! \n<b>Modified by:</b>\n
--! Erik van der Bij \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> v0.02 PAS Entity Ports added, start of architecture content
--! -> v0.03 EG timing changes; tx_clk_p_buff_i got 1 more bit
--! briefly byte_index_i needed to arrive 1 clock tick earlier
--! renamed from tx to tx_serializer
--
---------------------------------------------------------------------------------------------------
--
--! @todo -> comments!!
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_tx_serializer
--=================================================================================================
entity WF_tx_serializer is
generic (c_TX_CLK_BUFF_LGTH: natural);
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control
start_prod_p_i : in std_logic; --! indication that WF_engine_control is in prod_watchdog state
-- a correct ID_DAT asking for a produced var has been
-- received and ............
byte_ready_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication that it is the last byte of data
-- CRC bytes follow
-- Signals from the WF_prod_bytes_retriever
byte_i : in std_logic_vector (7 downto 0);
--! data byte to be delivered
-- Signal from the WF_rx_tx_osc
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
--! clk for transmission synchronization
-- OUTPUTS
-- Signal to the WF_engine_control
request_byte_p_o : out std_logic;
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; --! transmitter serial data
tx_enable_o : out std_logic --! transmitter enable
);
end entity WF_tx_serializer;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_tx_serializer is
type tx_state_t is (idle, send_fss, send_data_byte, send_crc_bytes, send_queue, stop_transmission);
signal tx_state, nx_tx_state : tx_state_t;
signal s_prepare_to_produce, s_sending_FSS : std_logic;
signal s_sending_data, s_sending_CRC : std_logic;
signal s_sending_QUEUE, s_start_crc_p : std_logic;
signal s_data_bit_to_crc_p :std_logic;
signal s_txd, s_decr_index_p : std_logic;
signal s_bit_index_load, s_decr_index : std_logic;
signal s_bit_index_is_zero, s_stop_transmission : std_logic;
signal s_bit_index, s_bit_index_top : unsigned(4 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_crc_bytes_manch : std_logic_vector (31 downto 0);
signal s_crc_bytes,s_data_byte_manch : std_logic_vector (15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Serializer's state machine: the state machine is divided in three parts (a clocked
--! process to store the current state, a combinatorial process to manage state transitions and
--! finally a combinatorial process to manage the output signals), which are the 3 processes that
--! follow.
--! The signal tx_clk_p_buff_i is used for the synchronization of the state transitions of the
--! machine as well as of the actions on the output signals.
-- The following drawing shows the transitions of the signal tx_clk_p_buff_i with respect to
-- the signal tx_clk (line driver half bit clock).
-- tx_clk: __________|----------------|________________|----------------|_______________
-- tx_clk_p_buff (3): |0|0|0|1 |0|0|0|1
-- tx_clk_p_buff (2): |0|0|1|0 |0|0|1|0
-- tx_clk_p_buff (1): |0|1|0|0 |0|1|0|0
-- tx_clk_p_buff (0): |1|0|0|0 |1|0|0|0
-- tx states analysis:
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "idle state": signals initializations
-- jump to "send_fss" state after a pulse on the signal start_prod_p_i (controlled by the
-- WF_engine_control)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_fss" state: delivery of the manchester encoded bits of the Frame Start Sequence (including
-- preamble and Frame Start delimiter).
-- 32 bits to be sent (2 encoded bytes)
-- bit delivery starts after each tx_clk_p_buff (1) assertion (Bits_Delivery process)
-- the s_bit_index is updated after each tx_clk_p_buff (3) assertion (s_bit_index is ahead of the
-- bit being sent)
-- jump to "send_data_byte" state after the beginning of the 32nd bit delivery and after
-- the tx_clk_p_buff(3) assertion.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_data_byte" state: delivery of manchester encoded bits of data that arrive from the
-- WF_prod_bytes_retriever unit (byte_i), with the coordination of the WF_engine_control (byte_ready_p_i)
-- request of a new byte on tx_clk_p_buff (0) assertion (with s_bit_index = 0)
-- bit delivery after tx_clk_p_buff (1) assertion
-- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1))
-- s_bit_index updated after tx_clk_p_buff (3) assertion (the s_bit_index here loops several times
-- (between 0 and 16 for each byte, until the
-- last_byte_p_i gives a pulse)
-- the first data byte from the WF_prod_bytes_retriever unit is already available after the assertion of the
-- start_prod_p_i signal; for the rest, there is a request of a new byte when the s_bit_index
-- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal
-- triggers the WF_control_engine to send a new address to the memory of the produced_vars unit (new
-- address available on tx_clk_p_buff (1)), which in turn will give an output one uclk cycle later
-- (on tx_clk_p_buff (2)), exactly on the assertion of the byte_ready_p_i. Finally the first bit of
-- this new byte starts being delivered after tx_clk_p_buff (3) assertion.
-- jump to "send_crc_bytes" state after the arrival of the last_byte_p_i pulse (on the
-- tx_clk_p_buff (2), along with the byte_ready_p_i). Differently than in the previous case, now
-- the state transition takes place after the tx_clk_p_buff (2) assertion. This is essential in
-- order to force the s_bit_index (which is updated after tx_clk_p_buff(3) assertion) to the
-- s_bit_index_top indicated by the "send_crc_bytes" state (31 bits) and not to the one of the
-- "send_data_byte" state (16 bits).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_crc_bytes" state: delivery of the two manchester encoded bytes that come out of the CRC
-- calculator unit (2 bytes).
-- bit delivery starts after each tx_clk_p_buff (1) assertion (Bits_Delivery process)
-- the s_bit_index is updated after each tx_clk_p_buff (3) assertion (s_bit_index is ahead of the
-- bit being sent)
-- jump to "send_queue" state after the arrival of the last_byte_p_i pulse (on the tx_clk_p_buff(2)
-- along with the byte_ready_p_i). As before, the state transition is essential before the update
-- of the s_bit_index
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Receiver_FSM_Sync:
Transmitter_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_state <= idle;
else
tx_state <= nx_tx_state;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process Transmitter_FSM_Comb_State_Transitions:
--! definition of the state transitions of the FSM
Transmitter_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
start_prod_p_i, tx_clk_p_buff_i)
begin
nx_tx_state <= idle;
case tx_state is
when idle =>
if start_prod_p_i = '1' then
nx_tx_state <= send_fss;
else
nx_tx_state <= idle;
end if;
when send_fss =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1' then
nx_tx_state <= send_data_byte;
else
nx_tx_state <= send_fss;
end if;
when send_data_byte =>
if last_byte_p_i = '1' then
nx_tx_state <= send_crc_bytes;
else
nx_tx_state <= send_data_byte;
end if;
when send_crc_bytes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= send_queue;
else
nx_tx_state <= send_crc_bytes;
end if;
when send_queue =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= stop_transmission;
else
nx_tx_state <= send_queue;
end if;
when stop_transmission =>
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= stop_transmission;
end if;
when others =>
nx_tx_state <= idle;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process Transmitter_FSM_Comb_Output_Signals:
--! definition of the output signals of the FSM
Transmitter_FSM_Comb_Output_Signals: process ( tx_state )
begin
case tx_state is
when idle =>
-- initializations
s_decr_index <= '0';
s_prepare_to_produce <= '1';
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when send_fss =>
s_decr_index <= '0';
s_prepare_to_produce <= '0';
s_sending_FSS <= '1';
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when send_data_byte =>
s_decr_index <= '0';
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '1';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when send_crc_bytes =>
s_decr_index <= '0';
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '1';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when send_queue =>
s_decr_index <= '0';
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '1';
s_stop_transmission <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when stop_transmission =>
s_decr_index <= '0';
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '1';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
s_decr_index <= '0';
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
--@brief Instantiation of a manchester encoder for a data byte (8 bits long)
data_byte_manc_encoder: WF_manch_encoder
generic map(word_length => 8)
port map(
word_i => s_byte,
word_manch_o => s_data_byte_manch
);
---------------------------------------------------------------------------------------------------
--@brief Instantiation of a manchester encoder for the CRC bytes (16 bits long)
crc_bytes_manc_encoder: WF_manch_encoder
generic map(word_length => 16)
port map(
word_i => s_crc_bytes,
word_manch_o => s_crc_bytes_manch
);
---------------------------------------------------------------------------------------------------
--!@brief CRC calculator
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the CRC unit
crc_generation: WF_crc
generic map(
c_GENERATOR_POLY_length => 16)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
crc_o => s_crc_bytes,
crc_ok_p => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- concurrent signals assignement for the crc_generator inputs
s_start_crc_p <= s_sending_FSS and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
-- the CRC calculation starts when at the end of the FSS (beginning of data bytes delivery)
s_data_bit_to_crc_p <= s_sending_data and s_bit_index(0) and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
-- only the 1st part of a manchester encoded bit goes to the CRC calculator
---------------------------------------------------------------------------------------------------
--@brief Managment of the pointer that indicates which bit of a manchester encoded byte is to be
--! delivered. According to the state of the FSM, a byte may be a FSS one, or a data byte or a
--! CRC or a FES byte.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a bits counter:
Outgoing_Bits_Index: WF_decr_counter
generic map(g_counter_lgth => 5)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_index_p,
counter_o => s_bit_index,
counter_is_zero_o => s_bit_index_is_zero);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process that according to the state of the FSM sets the values to the
-- Outgoing_Bits_Index inputs
Bit_Index: process (s_prepare_to_produce,s_sending_FSS, s_sending_data, s_sending_crc,
s_sending_QUEUE, s_bit_index_is_zero,tx_clk_p_buff_i)
begin
if s_prepare_to_produce ='1' then
s_bit_index_top <= to_unsigned (FSS'length - 1, s_bit_index'length);
s_bit_index_load <= '1';
s_decr_index_p <= '0';
elsif s_sending_FSS = '1' then
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_data = '1' then
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_crc = '1' then
s_bit_index_top <= to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_QUEUE = '1' then
s_bit_index_top <= to_unsigned (FES'length - 1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
else
s_bit_index_top <= to_unsigned (FSS'length - 1, s_bit_index'length);
s_bit_index_load <= '0';
s_decr_index_p <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--!@brief Instantiation of the unit that according to the state of the FSM and the
--! bits index counter, outputs FSS, data, CRC or FES manchester encoded bits to the txd_o.
--! The unit also and manages the tx_enable_o signal.
bits_to_txd: WF_bits_to_txd
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch,
sending_fss_i => s_sending_FSS,
sending_data_i => s_sending_data,
sending_crc_i => s_sending_crc,
sending_fes_i => s_sending_queue,
stop_transmission_i => s_stop_transmission,
tx_clk_p_i => tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-3),
txd_o => s_txd,
tx_enable_o => tx_enable_o);
--------------------------------------------------------------------------------------------------
Input_Byte_Sampling: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_byte <= (others => '0');
else
if byte_ready_p_i = '1' then
s_byte <= byte_i;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
tx_data_o <= s_txd;
request_byte_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
-- request for a new byte from the WF_prod_bytes_retriever unit (passing from WF_engine_control)
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------===============================================================================================
-- architecture end
--=======================================================
\ No newline at end of file
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_tx_serializer.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx_serializer --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: WF_tx_serializer
--
--
--! @brief The unit is generating the nanoFIP FIELDRIVE outputs FD_TXD and FD_TXENA. It is
--! retreiving bytes of data from:
--! o the WF_prod_bytes_retriever (from the Ctrl until the MPS)
--! o WF_package (FSS, FES)
--! o and the WF_CRC (CRC bytes).
--! It encodes the bytes to the Manchester 2 scheme and outputs one by one the encoded
--! bits on the moments indicated by the tx_clk_p_buff signal.
--! After the delivery of a byte, it is requesting from the WF_engine_control for a new
--! one and it is the WF_engine_control that keeps track of the amount of bytes been
--! sent.
--!
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 07/2010
--
--
--! @version v0.03
--
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_engine_control \n
--! WF_prod_bytes_retriever \n
--! WF_rx_tx_osc \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> v0.02 PAS Entity Ports added, start of architecture content
--! -> v0.03 EG timing changes; tx_clk_p_buff_i got 1 more bit
--! briefly byte_index_i needed to arrive 1 clock tick earlier
--! renamed from tx to tx_serializer
--
---------------------------------------------------------------------------------------------------
--
--! @todo ->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_tx_serializer
--=================================================================================================
entity WF_tx_serializer is
generic (c_TX_CLK_BUFF_LGTH: natural);
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_prod_bytes_retriever
byte_i : in std_logic_vector (7 downto 0); --! data byte to be delivered
-- Signals from the WF_engine_control
start_prod_p_i : in std_logic; --! indication for the start of the production
byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
-- Signal from the WF_rx_tx_osc
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
--! clk for the transmission synchronization
-- OUTPUTS
-- Signal to the WF_engine_control unit
byte_request_p_o : out std_logic;
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; --! transmitter serial data
tx_enable_o : out std_logic --! transmitter enable
);
end entity WF_tx_serializer;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_tx_serializer is
type tx_state_t is (idle, send_fss,send_data_byte,send_crc_bytes,send_queue,stop_transmission);
signal tx_state, nx_tx_state : tx_state_t;
signal s_prepare_to_produce, s_sending_FSS, s_sending_data, s_sending_CRC : std_logic;
signal s_sending_QUEUE, s_start_crc_p, s_data_bit_to_crc_p, s_stop_transmission : std_logic;
signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero, s_tx_enable : std_logic;
signal s_bit_index, s_bit_index_top : unsigned(4 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_crc_bytes_manch : std_logic_vector(31 downto 0);
signal s_crc_bytes,s_data_byte_manch : std_logic_vector(15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Serializer's FSM --
---------------------------------------------------------------------------------------------------
--!@brief Serializer's state machine: the state machine is divided in three parts (a clocked
--! process to store the current state, a combinatorial process to manage state transitions and
--! finally a combinatorial process to manage the output signals), which are the 3 processes that
--! follow.
--! The signal tx_clk_p_buff_i is used for the synchronization of the state transitions of the
--! machine as well as of the actions on the output signals.
-- The following drawing shows the transitions of the signal tx_clk_p_buff_i with respect to
-- the signal tx_clk (line driver half bit clock).
-- tx_clk: __________|----------------|________________|----------------|_______________
-- tx_clk_p_buff (3): |0|0|0|1 |0|0|0|1
-- tx_clk_p_buff (2): |0|0|1|0 |0|0|1|0
-- tx_clk_p_buff (1): |0|1|0|0 |0|1|0|0
-- tx_clk_p_buff (0): |1|0|0|0 |1|0|0|0
-- tx states analysis:
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "idle state": signals initializations
-- jump to "send_fss" state after a pulse on the signal start_prod_p_i (controlled by the
-- WF_engine_control)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_fss" state: delivery of the manchester encoded bits of the Frame Start Sequence (including
-- preamble and Frame Start delimiter).
-- 32 bits to be sent (2 encoded bytes)
-- bit delivery starts after each tx_clk_p_buff (1) assertion (Bits_Delivery process)
-- the s_bit_index is updated after each tx_clk_p_buff (3) assertion (s_bit_index is ahead of the
-- bit being sent)
-- jump to "send_data_byte" state after the beginning of the 32nd bit delivery and after
-- the tx_clk_p_buff(3) assertion.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_data_byte" state: delivery of manchester encoded bits of data that arrive from the
-- WF_prod_bytes_retriever unit (byte_i), with the coordination of the WF_engine_control (byte_request_accept_p_i)
-- request of a new byte on tx_clk_p_buff (0) assertion (with s_bit_index = 0)
-- bit delivery after tx_clk_p_buff (1) assertion
-- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1))
-- s_bit_index updated after tx_clk_p_buff (3) assertion (the s_bit_index here loops several times
-- (between 0 and 16 for each byte, until the
-- last_byte_p_i gives a pulse)
-- the first data byte from the WF_prod_bytes_retriever unit is already available after the assertion of the
-- start_prod_p_i signal; for the rest, there is a request of a new byte when the s_bit_index
-- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal
-- triggers the WF_control_engine to send a new address to the memory of the produced_vars unit (new
-- address available on tx_clk_p_buff (1)), which in turn will give an output one uclk cycle later
-- (on tx_clk_p_buff (2)), exactly on the assertion of the byte_request_accept_p_i. Finally the first bit of
-- this new byte starts being delivered after tx_clk_p_buff (3) assertion.
-- jump to "send_crc_bytes" state after the arrival of the last_byte_p_i pulse (on the
-- tx_clk_p_buff (2), along with the byte_request_accept_p_i). Differently than in the previous case, now
-- the state transition takes place after the tx_clk_p_buff (2) assertion. This is essential in
-- order to force the s_bit_index (which is updated after tx_clk_p_buff(3) assertion) to the
-- s_bit_index_top indicated by the "send_crc_bytes" state (31 bits) and not to the one of the
-- "send_data_byte" state (16 bits).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_crc_bytes" state: delivery of the two manchester encoded bytes that come out of the CRC
-- calculator unit (2 bytes).
-- bit delivery starts after each tx_clk_p_buff (1) assertion (Bits_Delivery process)
-- the s_bit_index is updated after each tx_clk_p_buff (3) assertion (s_bit_index is ahead of the
-- bit being sent)
-- jump to "send_queue" state after the arrival of the last_byte_p_i pulse (on the tx_clk_p_buff(2)
-- along with the byte_request_accept_p_i). As before, the state transition is essential before the update
-- of the s_bit_index
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Serializer_FSM_Sync:
Serializer_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_state <= idle;
else
tx_state <= nx_tx_state;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process Serializer_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM
Serializer_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
start_prod_p_i, tx_clk_p_buff_i)
begin
nx_tx_state <= idle;
case tx_state is
when idle =>
if start_prod_p_i = '1' then
nx_tx_state <= send_fss;
else
nx_tx_state <= idle;
end if;
when send_fss =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1' then
nx_tx_state <= send_data_byte;
else
nx_tx_state <= send_fss;
end if;
when send_data_byte =>
if last_byte_p_i = '1' then
nx_tx_state <= send_crc_bytes;
else
nx_tx_state <= send_data_byte;
end if;
when send_crc_bytes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= send_queue;
else
nx_tx_state <= send_crc_bytes;
end if;
when send_queue =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= stop_transmission;
else
nx_tx_state <= send_queue;
end if;
when stop_transmission =>
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= stop_transmission;
end if;
when others =>
nx_tx_state <= idle;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process Serializer_FSM_Comb_Output_Signals: definition of the output
--! signals of the FSM
Serializer_FSM_Comb_Output_Signals: process ( tx_state )
begin
case tx_state is
when idle =>
----------------------------------
s_prepare_to_produce <= '1';
----------------------------------
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
when send_fss =>
s_prepare_to_produce <= '0';
----------------------------------
s_sending_FSS <= '1';
----------------------------------
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
when send_data_byte =>
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
----------------------------------
s_sending_data <= '1';
----------------------------------
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
when send_crc_bytes =>
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '0';
----------------------------------
s_sending_CRC <= '1';
----------------------------------
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
when send_queue =>
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '0';
----------------------------------
s_sending_QUEUE <= '1';
----------------------------------
s_stop_transmission <= '0';
when stop_transmission =>
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
----------------------------------
s_stop_transmission <= '1';
----------------------------------
when others =>
s_prepare_to_produce <= '0';
s_sending_FSS <= '0';
s_sending_data <= '0';
s_sending_CRC <= '0';
s_sending_QUEUE <= '0';
s_stop_transmission <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- Input Byte Retrieval --
---------------------------------------------------------------------------------------------------
Input_Byte_Retrieval: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_byte <= (others => '0');
else
if byte_request_accept_p_i = '1' then
s_byte <= byte_i;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Manchester Encoding --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--@brief Instantiation of a manchester encoder for a data byte (8 bits long)
data_byte_manc_encoder: WF_manch_encoder
generic map(word_length => 8)
port map(
word_i => s_byte,
word_manch_o => s_data_byte_manch
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--@brief Instantiation of a manchester encoder for the CRC bytes (16 bits long)
crc_bytes_manc_encoder: WF_manch_encoder
generic map(word_length => 16)
port map(
word_i => s_crc_bytes,
word_manch_o => s_crc_bytes_manch
);
---------------------------------------------------------------------------------------------------
-- CRC calculation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of the CRC unit
crc_generation: WF_crc
generic map(
c_GENERATOR_POLY_length => 16)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
crc_o => s_crc_bytes,
crc_ok_p => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- concurrent signals assignement for the crc_generator inputs
s_start_crc_p <= s_sending_FSS and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
-- the CRC calculation starts when at the end of the FSS (beginning of data bytes delivery)
s_data_bit_to_crc_p <= s_sending_data and s_bit_index(0) and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
-- only the 1st part of a manchester encoded bit goes to the CRC calculator
---------------------------------------------------------------------------------------------------
-- Bits delivery --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--@brief Managment of the pointer that indicates which bit of a manchester encoded byte is to be
--! delivered. According to the state of the FSM, a byte may be a FSS one, or a data byte or a
--! CRC or a FES byte.
Outgoing_Bits_Index: WF_decr_counter
generic map(g_counter_lgth => 5)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_index_p,
-----------------------------------------------
counter_o => s_bit_index,
counter_is_zero_o => s_bit_index_is_zero);
-----------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process that according to the state of the FSM sets the values to the
-- Outgoing_Bits_Index inputs.
Bit_Index: process (s_prepare_to_produce,s_sending_FSS, s_sending_data, s_sending_crc,
s_sending_QUEUE, s_bit_index_is_zero,tx_clk_p_buff_i)
begin
if s_prepare_to_produce ='1' then
s_bit_index_top <= to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_load <= '1';
s_decr_index_p <= '0';
elsif s_sending_FSS = '1' then -- sending the 16 FSS manch. bits
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_data = '1' then -- sending bytes of 16 manch. bits
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_crc = '1' then -- sending the 32 manch. CRC bits
s_bit_index_top <= to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_QUEUE = '1' then -- sending the 16 manch. FSS
s_bit_index_top <= to_unsigned (c_FES'length - 1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
else
s_bit_index_top <= to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_load <= '0';
s_decr_index_p <= '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of the unit that according to the state of the FSM and the
--! bits index counter, outputs FSS, data, CRC or FES manchester encoded bits to the txd_o.
--! The unit also generates the tx_enable_o signal.
bits_to_txd: WF_bits_to_txd
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch,
sending_fss_i => s_sending_FSS,
sending_data_i => s_sending_data,
sending_crc_i => s_sending_crc,
sending_fes_i => s_sending_queue,
stop_transmission_i => s_stop_transmission,
tx_clk_p_i => tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-3),
---------------------------------------------
txd_o => s_txd,
tx_enable_o => s_tx_enable);
---------------------------------------------
---------------------------------------------------------------------------------------------------
-- Outputs --
---------------------------------------------------------------------------------------------------
tx_data_o <= s_txd;
tx_enable_o <= s_tx_enable;
byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
-- request for a new byte from the WF_prod_bytes_retriever unit (passing from WF_engine_control)
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
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