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nanoFIP - Gateware
Commit 15122c97 authored by egousiou's avatar egousiou
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new unit WF_wb_controller.vhd 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@116 7f0067c9-7624-46c7-bd39-3fb5400c0213
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DualClkRAM.vhd
View file @ 15122c97
......@@ -49,10 +49,10 @@ use PROASIC3.all;
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! ProASIC3 lib \n
--! ProASIC3 lib \n
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......
NanoFip.pdc
View file @ 15122c97
......@@ -573,6 +573,8 @@ set_io r_fcser_o \
-pinname 85 \
-fixed yes \
-DIRECTION Output
#
# Non IO constraints
#
......
WF_wb_controller.vhd 0 → 100644
View file @ 15122c97
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_wb_controller.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_wb_controller --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to
--! the user's STBs.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 20/01/2011
--
--
--! @version v0.01
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_production \n
--! WF_consumption \n
--
---------------------------------------------------------------------------------------------------
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! \n\n<b>Last changes:</b>\n
--! ->
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 1, 3, 4 of var_i(0 to 6) are unused" --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_wb_controller
--=================================================================================================
entity WF_wb_controller is
port (
-- INPUTS
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_rst_i : in std_logic; --! WISHBONE reset
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_stb_r_edge_p_i : in std_logic; --! rising edge on WISHBONE strobe
wb_we_i : in std_logic; --! WISHBONE write enable
wb_adr_id_i : in std_logic_vector (2 downto 0); --! 3 first bits of WISHBONE address
-- OUTPUTS
-- Signal from the WF_production_unit
wb_ack_prod_p_o : out std_logic; --! response to a write cycle
-- latching moment of wb_dat_i
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_p_o : out std_logic --! WISHBONE acknowledge
-- response to master's strobe
);
end entity WF_wb_controller;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_ack_write_p_d, s_wb_ack_read_p_d : std_logic;
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Generate_wb_ack_write_p_o: Generation of the wb_ack_write_p signal
--! (acknowledgement from WISHBONE Slave of the write cycle, as a response to the master's storbe).
--! The 1 wb_clk-wide pulse is generated if the wb_cyc and wb_we are asserted and the WISHBONE input
--! address corresponds to an address in the Produced memory block.
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_id_i = "010") and
(wb_we_i = '1') and
(wb_cyc_i = '1'))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Generate_wb_ack_read_p: Generation of the wb_ack_read_p signal
--! (acknowledgement from WISHBONE Slave of the read cycle, as a response to the master's strobe).
--! The 1 wb_clk-wide pulse is generated if the wb_cyc is asserted and the WISHBONE input address
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_id_i(1 downto 0) = "00") and
(wb_cyc_i = '1'))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Output_Register:
WB_ACK: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then
s_wb_ack_read_p_d <= '0';
s_wb_ack_write_p_d <= '0';
else
s_wb_ack_read_p_d <= s_wb_ack_read_p;
s_wb_ack_write_p_d <= s_wb_ack_write_p;
end if;
end if;
end process;
wb_ack_p_o <= s_wb_ack_read_p_d or s_wb_ack_write_p_d;
wb_ack_prod_p_o <= s_wb_ack_write_p_d;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
nanofip.vhd
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tmp_snippets.txt deleted 100644 → 0
View file @ 63cac757
--3456789-123456789-123456789-123456789-123456789-123456789-123456789-123456789
--! test for parity
component PARITY
port (A: in std_logic_vector (7 downto 0); --! test for parity: input byte
ODD: out std_logic); --! output bit
end component;
--! Architecture contains only connectivity
architecture struc of nanofip is
begin
--! It should be documented now
par1: PARITY --! my dummy parity to let block appear
port map (); --! I think it's documented now
end par1;
end a1;
-------------------------------------------------------------------------------
-- E N D O F F I L E
-------------------------------------------------------------------------------
tmp_wf_reset_unit_with_PoR.vhd deleted 100644 → 0
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wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ 15122c97
......@@ -46,11 +46,11 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! DualClkRAM.vhd \n
--! DualClkRAM.vhd \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_bits_to_txd.vhd
View file @ 15122c97
......@@ -46,13 +46,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_tx_rx_osc \n
--! WF_tx_serializer \n
--! WF_reset_unit \n
--! WF_tx_rx_osc \n
--! WF_tx_serializer \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -142,7 +142,7 @@ begin
if tx_clk_p_i = '1' then
if sending_fss_i = '1' then
txd_o <= FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize)
txd_o <= c_FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize)
elsif sending_data_i = '1' then
txd_o <= data_byte_manch_i (to_integer (resize(txd_bit_index_i, 4))); -- 1 data-byte
......@@ -151,7 +151,7 @@ begin
txd_o <= crc_byte_manch_i (to_integer (txd_bit_index_i)); -- CRC: 2 bytes long
elsif sending_fes_i = '1' then
txd_o <= FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
else
txd_o <= '0';
......@@ -179,10 +179,10 @@ begin
if ((sending_fss_i = '1') or (sending_data_i = '1') or -- tx sending bits
(sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then
if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enabble with the
end if; -- the delivery of the 1st FSS bit
-- txd :________|-----|___________|--------
if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enabble with the
end if; -- the delivery of the 1st FSS bit
-- txd (FSS) :________|-----|___________|--------
-- tx_clk_p_buff(1):______|-|___|-|___|-|___|-|___|-|__
-- sending_FSS :___|-------------------------------
-- tx_enable :________|--------------------------
......
wf_cons_bytes_processor.vhd
View file @ 15122c97
......@@ -61,24 +61,25 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 15/12/2010
--! @date 15/12/2010
--
--
--! @version v0.03
--! @version v0.03
--
--
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_engine_control \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/09/2009 v0.01 EB First version \n
......@@ -119,11 +120,9 @@ port (
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address to memory
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_stb_r_edge_p_i : in std_logic; --! pulse on the rising edge of stb_i
wb_adr_i : in std_logic_vector (8 downto 0); --! WISHBONE address to memory
-- Signals from the WF_rx_deserializer unit
byte_i : in std_logic_vector (7 downto 0); --! input byte
......@@ -138,9 +137,8 @@ port (
-- OUTPUTS
-- nanoFIP User Interface, WISHBONE Slave outputs
-- nanoFIP User Interface, WISHBONE Slave output
data_o : out std_logic_vector (15 downto 0);--! data out bus
wb_ack_cons_p_o : out std_logic; --! WISHBONE acknowledge
-- Signals to the WF_cons_frame_validator unit
cons_ctrl_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT Control byte
......@@ -203,18 +201,6 @@ begin
data_portb_i => byte_i, -- byte to be written
write_en_portb_i => s_write_byte_to_mem_p ); -- write enable
---------------------------------------------------------------------------------------------------
--!@brief Generate_wb_ack_cons_p_o: Generation of the wb_ack_cons_p_o signal
--! (acknowledgement from WISHBONE Slave of the read cycle, as a response to the master's strobe).
--! wb_ack_cons_p_o is 1 wclk-wide pulse asserted 3 wclk cycles after the assertion of the
--! asynchronous strobe signal, if the wb_cyc is asserted and the WISHBONE input address
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_cons_p_o: wb_ack_cons_p_o <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 8) = "00") and
(wb_cyc_i = '1'))
else '0';
---------------------------------------------------------------------------------------------------
......
wf_cons_bytes_to_dato.vhd
View file @ 15122c97
......@@ -51,12 +51,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_cons_bytes_processor \n
--! WF_reset_unit \n
--! WF_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_cons_outcome.vhd
View file @ 15122c97
......@@ -46,11 +46,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_enginr_control \n
--! WF_cons_frame_validator \n
--! WF_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_consumption.vhd
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wf_crc.vhd
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......@@ -45,14 +45,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_tx_serializer \n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_tx_serializer \n
--
--
--! \n<b>Modified by:</b> \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_engine_control.vhd
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wf_inputs_synchronizer.vhd
View file @ 15122c97
......@@ -27,10 +27,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit synchronises all the input signals with to the uclk or wb_clk, to be used
-- by all the other units of nanoFIP; a set of 3ple buffers is used for each signal.
-- Note: Because of the 3ple buffering, transitions on input signals of less than 2
-- clk cycles are not considered.
--! @brief The unit synchronises all the input signals with to the uclk or wb_clk, to be used
-- by all the other units of nanoFIP; a set of 3ple buffers is used for each signal.
-- Note: Because of the 3ple buffering, transitions on input signals of less than 2
-- clk cycles are not considered.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......@@ -45,12 +45,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -99,16 +99,15 @@ entity WF_inputs_synchronizer is
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
dat_a_i : in std_logic_vector(15 downto 0);
wb_adr_a_i : in std_logic_vector(9 downto 0);
wb_cyc_a_i : in std_logic;
wb_rst_a_i : in std_logic; --! WISHBONE reset
wb_stb_a_i : in std_logic;
wb_we_a_i : in std_logic;
-- nanoFIP User Interface, non WISHBONE
-- nanoFIP User Interface, NON WISHBONE
dat_a_i : in std_logic_vector(15 downto 0);
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
......@@ -125,7 +124,6 @@ entity WF_inputs_synchronizer is
nostat_o : out std_logic;
rstin_o : out std_logic;
slone_o : out std_logic;
rstin_f_edge_o : out std_logic;
-- nanoFIP WorldFIP Settings
c_id_o : out std_logic_vector(3 downto 0);
......@@ -135,15 +133,13 @@ entity WF_inputs_synchronizer is
subs_o : out std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
wb_adri_o : out std_logic_vector(9 downto 0);
wb_cyc_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_we_o : out std_logic;
-- nanoFIP User Interface, non WISHBONE
-- nanoFIP User Interface, NON WISHBONE
slone_dati_o : out std_logic_vector(15 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
......@@ -173,12 +169,10 @@ architecture rtl of WF_inputs_synchronizer is
signal s_mid_d1, s_mid_d2, s_mid_d3, s_cid_d1, s_cid_d2, s_cid_d3 : std_logic_vector(3 downto 0);
signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3, s_fd_rxcdn_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3 : std_logic_vector(2 downto 0);
signal s_u_rst_d3 : std_logic_vector(3 downto 0);
signal s_u_rst_d3 : std_logic_vector(2 downto 0);
signal s_nostat_d3, s_slone_d3 : std_logic_vector(2 downto 0);
signal s_wb_adr_d1, s_wb_adr_d2, s_wb_adr_d3 : std_logic_vector(9 downto 0);
signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0);
signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0);
signal s_wb_dati_d1, s_wb_dati_d2, s_wb_dati_d3 : std_logic_vector(7 downto 0);
signal s_slone_dati_d1, s_slone_dati_d3, s_slone_dati_d2 :std_logic_vector(15 downto 0);
......@@ -192,12 +186,11 @@ begin
RSTIN_synchronisation_with_uclk: process (uclk_i)
begin
if rising_edge (uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (2 downto 0) & rstin_a_i;
s_u_rst_d3 <= s_u_rst_d3 (1 downto 0) & rstin_a_i;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rstin_o <= s_u_rst_d3(2);
rstin_f_edge_o <= s_u_rst_d3(3) and (not s_u_rst_d3(2));
---------------------------------------------------------------------------------------------------
......@@ -293,12 +286,6 @@ begin
begin
if rising_edge (wb_clk_i) then
if wb_rst_a_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_dati_d1 <= (others => '0');
s_wb_dati_d2 <= (others => '0');
s_wb_dati_d3 <= (others => '0');
s_wb_adr_d1 <= (others => '0');
s_wb_adr_d2 <= (others => '0');
s_wb_adr_d3 <= (others => '0');
s_wb_stb_d1 <= '0';
s_wb_stb_d2 <= '0';
s_wb_stb_d3 <= '0';
......@@ -310,14 +297,6 @@ begin
s_wb_cyc_d3 <= '0';
else
s_wb_dati_d3 <= s_wb_dati_d2;
s_wb_dati_d2 <= s_wb_dati_d1;
s_wb_dati_d1 <= dat_a_i (7 downto 0);
s_wb_adr_d3 <= s_wb_adr_d2;
s_wb_adr_d2 <= s_wb_adr_d1;
s_wb_adr_d1 <= wb_adr_a_i;
s_wb_stb_d1 <= wb_stb_a_i;
s_wb_stb_d2 <= s_wb_stb_d1;
s_wb_stb_d3 <= s_wb_stb_d2;
......@@ -335,8 +314,6 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- --
wb_dati_o <= s_wb_dati_d3;
wb_adri_o <= s_wb_adr_d3;
wb_cyc_o <= s_wb_cyc_d3;
wb_we_o <= s_wb_we_d3;
wb_stb_o <= s_wb_stb_d3;
......
wf_manch_code_viol_check.vhd
View file @ 15122c97
......@@ -62,12 +62,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx_deglitcher \n
--! WF_reset_unit \n
--! WF_rx_deglitcher \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_manch_encoder.vhd
View file @ 15122c97
......@@ -47,7 +47,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! \n<b>Modified by:</b> \n
--! Evangelia Gousiou \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_model_constr_decoder.vhd
View file @ 15122c97
......@@ -52,12 +52,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit\n
--! WF_reset_unit\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_package.vhd
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This diff is collapsed.
wf_prod_bytes_retriever.vhd
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wf_prod_bytes_to_dati.vhd
View file @ 15122c97
......@@ -45,12 +45,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_reset_unit \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_prod_data_lgth_calc.vhd
View file @ 15122c97
......@@ -57,11 +57,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_prod_permit.vhd
View file @ 15122c97
......@@ -44,12 +44,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......
wf_production.vhd
View file @ 15122c97
This diff is collapsed.
wf_reset_unit.vhd
View file @ 15122c97
......@@ -146,7 +146,6 @@ entity WF_reset_unit is
uclk_i : in std_logic; --! 40 MHz clock
rstin_i : in std_logic; --! initialisation control, active low
rstpon_i : in std_logic; --! Power On Reset, active low
rstin_f_edge_i : in std_logic; --! rising edge on RSTIN
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_engine_control unit
......@@ -252,16 +251,15 @@ begin
--!@brief Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st,rstin_f_edge_i,
s_counter_is_ten,rstin_i,s_counter_is_four,
s_counter_is_full)
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, rstin_i, s_counter_is_four,
s_counter_is_ten, s_counter_is_full)
begin
case rstin_st is
when idle =>
if rstin_i = '0' then -- RSTIN active
if rstin_i = '0' then -- RSTIN active
nx_rstin_st <= rstin_eval;
else
......@@ -269,7 +267,7 @@ begin
end if;
when rstin_eval =>
if rstin_i = '1' then -- RSTIN deactivated before the 8 cycles
if rstin_i = '1' then -- RSTIN deactivated
nx_rstin_st <= idle;
else
......@@ -606,19 +604,16 @@ free_counter: WF_incr_counter
---------------------------------------------------------------------------------------------------
nFIP_rst_o <= s_intern_rst_from_RSTIN or s_intern_rst_from_var_rst or s_por; -- nanoFIP internal
-- reset; resets
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_por);
-- reset; resets all
-- logic apart from
-- WISHBONE
Outputs_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (s_por = '1') or (s_intern_rst_from_RSTIN = '1') or (s_intern_rst_from_var_rst = '1') then
rston_o <= '1'; -- active low
else
rston_o <= not s_rston;
rston_o <= not s_rston;
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_por);
end if;
end if;
end process;
......
wf_rx_deglitcher.vhd
View file @ 15122c97
......@@ -47,7 +47,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
-- @date 23/08/2010
......@@ -59,13 +58,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_tx-_rx_osc \n
--! WF_reset_unit \n
--! WF_tx-_rx_osc \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_rx_deserializer.vhd
View file @ 15122c97
......@@ -98,12 +98,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! units WF_rx_manch_code_check and Incoming_Bits_Index created;
--! each manch bit of FES checked (bf was just each bit, so any D5 was FES)
--! code cleaned-up + commented.\n
--! -> 12/2010 v0.02 EG CRC_ok pulse transfered 16 bits later to match the FES;
--! -> 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES;
--! like this we confirm that the CRC_ok_p arrived just before the FES,
--! and any 2 bytes that could by chanche be seen as CRC, are neglected.
--! FSM data_field_byte state: redundant code removed:
--! "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle"
--! code(more!)cleaned-up
--! -> 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if
--! bytes with size different than 8 have preceeded.
--
---------------------------------------------------------------------------------------------------
--
......@@ -186,10 +188,10 @@ architecture rtl of WF_rx_deserializer is
fsd_field, switch_to_deglitched, data_fcs_fes_fields);
signal rx_st, nx_rx_st : rx_st_t;
signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok_p_d16 : std_logic;
signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok_p_d16 : std_logic;
signal s_fsd_last_bit, s_fes_wrong_bit, s_sample_manch_bit_p_d1 : std_logic;
signal s_fes_detected_p, s_fes_detection_window : std_logic;
signal s_manch_not_ok, s_switching_to_deglitched : std_logic;
signal s_fes_detected_p : std_logic;
signal s_manch_not_ok, s_switching_to_deglitched : std_logic;
signal s_receiving_fsd, s_receiving_bytes, s_receiving_pre : std_logic;
signal s_decr_manch_bit_index_p, s_manch_bit_index_load : std_logic;
signal s_manch_bit_index_is_zero, s_edge_outside_manch_window_p : std_logic;
......@@ -198,7 +200,7 @@ architecture rtl of WF_rx_deserializer is
signal s_manch_r_edge_p, s_manch_f_edge_p : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned(3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_CRC_ok_p_buff : std_logic_vector (14 downto 0);
signal s_CRC_ok_p_buff, s_arriving_fes : std_logic_vector (15 downto 0);
--=================================================================================================
......@@ -488,15 +490,15 @@ architecture rtl of WF_rx_deserializer is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FSD aux signals concurrent assignments:
s_fsd_bit <= s_receiving_fsd and FSD (to_integer(s_manch_bit_index));
s_fsd_bit <= s_receiving_fsd and c_FSD (to_integer(s_manch_bit_index));
s_fsd_last_bit <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor rxd_filtered_i) and sample_manch_bit_p_i;
-- FES aux signals concurrent assignments :
s_fes_bit <= s_receiving_bytes and FES (to_integer(s_manch_bit_index));
s_fes_bit <= s_receiving_bytes and c_FES (to_integer(s_manch_bit_index));
s_fes_wrong_bit <= (s_fes_bit xor rxd_filtered_i) and sample_manch_bit_p_i;
s_fes_detected_p <=s_fes_detection_window and sample_manch_bit_p_i and s_manch_bit_index_is_zero;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process that according to the state of the FSM sets values to the
......@@ -517,7 +519,7 @@ architecture rtl of WF_rx_deserializer is
s_decr_manch_bit_index_p <= '0';
elsif s_switching_to_deglitched = '1' then -- preparation for the FSD byte
s_manch_bit_index_top <= to_unsigned(FSD'left-1,s_manch_bit_index_top'length);
s_manch_bit_index_top <= to_unsigned(c_FSD'left-1,s_manch_bit_index_top'length);
-- FSD'left-1: bc the 1st bit of the FSD has been covered at the state PRE_field_f_edge
s_manch_bit_index_load <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_manch_bit_index_p <= '0';
......@@ -539,27 +541,26 @@ architecture rtl of WF_rx_deserializer is
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process FES_Detector: creation of a window that is activated at the
--! beginning of an incoming byte and stays active as long as 16 incoming manch. bits match the FES.
--!@brief Synchronous process FES_Detector: The s_arriving_fes register is storing the last 16
--! manch. encoded bits received and the s_fes_detected_p indicates weather they match the FES.
FES_Detector: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fes_detection_window <= '1';
s_arriving_fes <= (others =>'0');
else
if s_manch_bit_index_is_zero = '1' and sample_manch_bit_p_i = '1' then
s_fes_detection_window <= '1';
elsif s_fes_wrong_bit = '1' then
s_fes_detection_window <= '0';
if s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
s_arriving_fes <= s_arriving_fes (14 downto 0) & rxd_filtered_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_fes_detected_p <= '1' when s_arriving_fes = (c_FES) and sample_manch_bit_p_i = '1' else '0';
......@@ -597,7 +598,7 @@ architecture rtl of WF_rx_deserializer is
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that manages the s_manch_code_viol_p signal: If at any point after
--!@brief Synchronous process that handles the s_manch_code_viol_p signal: If at any point after
--! the FSS and before the FES a code violation appears, the signal s_manch_not_ok stays
--! asserted until the end of the corresponding frame.
......@@ -613,22 +614,21 @@ architecture rtl of WF_rx_deserializer is
s_manch_not_ok <= '0';
else
if s_manch_code_viol_p ='1' and s_fes_wrong_bit ='1' then
s_manch_not_ok <= '1'; -- if a code violation appears
-- that doesn't belong to the FES
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that manages the signal crc_ok_p: The crc_ok_p coming from the CRC
--! calculator unit is delayed for 16 manch. encoded bits. The matching of this delayed pulse with
--! the FES pulse (s_fes_detected_p), would confirm that the two last bytes received before the
--! FES were the correct CRC.
--!@brief Synchronous process that handles the CRC signal: The crc_ok_p coming from the CRC
--! calculator unit is delayed for 16 manch. encoded bits. The matching of this delayed pulse
--! with the end of frame pulse (s_fes_detected_p), would confirm that the two last bytes
--! received before the FES were the correct CRC.
CRC_OK_pulse_delay: process (uclk_i)
begin
......@@ -644,22 +644,19 @@ architecture rtl of WF_rx_deserializer is
s_CRC_ok_p_buff <= (others => '0');
else
if s_sample_manch_bit_p_d1 = '1' then -- a delay is added to s_CRC_ok_p with
-- each manch. bit arrival. In total 15
-- delays have to be added in order to
-- arrive to the FES.
s_CRC_ok_p_buff <= s_CRC_ok_p_buff(13 downto 0) & s_CRC_ok_p;
-- a delay is added to s_CRC_ok_p with
if s_sample_manch_bit_p_d1 = '1' then -- each manch. bit arrival. In total 15
-- delays have to be added in order to
-- arrive to the FES.
s_CRC_ok_p_buff <= s_CRC_ok_p_buff(14 downto 0) & s_CRC_ok_p;
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(14); -- pulse 1 half-bit-clock period long
-- -- -- -- -- -- -- -- -- -- --
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(15); -- pulse 1 half-bit-clock period long
......
wf_rx_tx_osc.vhd
View file @ 15122c97
......@@ -61,15 +61,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03
--
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_synchronizer \n
--! WF_rx_deserializer \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_synchronizer \n
--! WF_rx_deserializer\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......
wf_status_bytes_gen.vhd
View file @ 15122c97
......@@ -52,19 +52,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 10/01/2011
--! @date 10/01/2011
--
--
--! @version v0.03
--! @version v0.03
--
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_consumption \n
--! WF_bytes_retriever \n
--! WF_prod_permit \n
--! WF_reset_unit \n
--! WF_consumption \n
--! WF_bytes_retriever \n
--! WF_prod_permit \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......
wf_tx_serializer.vhd
View file @ 15122c97
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