change pulse width RESET carrier

0601a74a · Alén Arias Vázquez · 95355592 · 0601a74a
Commit 0601a74a authored Apr 04, 2024 by Alén Arias Vázquez 😎
Hide whitespace changes
Inline Side-by-side

Showing with 9 additions and 3 deletions

wf_reset_unit.vhd src/wf_reset_unit.vhd +9 -3

No files found.
--- a/src/wf_reset_unit.vhd
+++ b/src/wf_reset_unit.vhd
@@ -204,7 +204,8 @@ architecture rtl of wf_reset_unit is
  -- info needed to define the length of the FD_RSTN
  signal s_transm_period                              : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
  signal s_txck_four_periods                          : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
-
+  -- need to extend pulse to reset carrier
+  signal s_txck_32_periods                            : unsigned (c_2_PERIODS_COUNTER_LGTH+1 downto 0);

 --=================================================================================================
 --                                       architecture begin
@@ -220,6 +221,11 @@ begin
                                                                                   -- periods = 4
                                                                                   -- FD_TXCK periods

+  s_txck_32_periods <= resize(s_transm_period, s_txck_32_periods'length) sll 5;   -- # uclk ticks
+                                                                                  -- of 32 transm.
+                                                                                  -- periods = 64
+                                                                                  -- FD_TXCK periods
+

 ---------------------------------------------------------------------------------------------------
 --                                        Input Synchronizers                                    --
@@ -656,7 +662,7 @@ RSTIN_free_counter: wf_incr_counter
 -- s_var_rst_c_is_full will be activated and the FSM will be reset.

 free_counter: wf_incr_counter
-  generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
+  generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH+2)
  port map(
    uclk_i            => uclk_i,
    counter_reinit_i  => s_var_rst_c_reinit,
@@ -669,7 +675,7 @@ free_counter: wf_incr_counter
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  s_var_rst_c_is_seven <= '1' when s_var_rst_c = to_unsigned(7, s_var_rst_c'length) else '0';
  s_var_rst_c_is_three <= '1' when s_var_rst_c = to_unsigned(3, s_var_rst_c'length) else '0';
-  s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_four_periods -1             else '0';
+  s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_32_periods -1               else '0';