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nanoFIP - Gateware
Commit 0453029e authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎
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change pulse width RESET carrier

parent 95355592
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Showing with 13 additions and 6 deletions
src/wf_reset_unit.vhd
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......@@ -184,8 +184,9 @@ architecture rtl of wf_reset_unit is
type rstin_st_t is (IDLE, RSTIN_EVAL, nFIP_ON_FD_ON, nFIP_OFF_FD_ON, nFIP_OFF_FD_OFF);
signal rstin_st, nx_rstin_st : rstin_st_t;
-- RSTIN counter
signal s_rstin_c, s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_three : std_logic;
signal s_rstin_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH+1 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_three : std_logic;
signal s_rstin_c_is_seven, s_rstin_c_is_4txck : std_logic;
signal s_rstin_c_is_full : std_logic;
-- resets generated after a RSTIN
......@@ -195,7 +196,7 @@ architecture rtl of wf_reset_unit is
VAR_RST_nFIP_OFF_FD_ON_RSTON_ON, VAR_RST_nFIP_ON_FD_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF);
signal var_rst_st, nx_var_rst_st : var_rst_st_t;
-- var_rst counter
-- var_rst counter
signal s_var_rst_c_reinit, s_var_rst_c_is_three : std_logic;
signal s_var_rst_c_is_seven, s_var_rst_c_is_4txck : std_logic;
signal s_var_rst_c_is_full : std_logic;
......@@ -204,7 +205,8 @@ architecture rtl of wf_reset_unit is
-- info needed to define the length of the FD_RSTN
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
-- need to extend pulse to reset carrier
signal s_txck_32_periods : unsigned (c_2_PERIODS_COUNTER_LGTH+1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -220,6 +222,11 @@ begin
-- periods = 4
-- FD_TXCK periods
s_txck_32_periods <= resize(s_transm_period, s_txck_32_periods'length) sll 5; -- # uclk ticks
-- of 32 transm.
-- periods = 64
-- FD_TXCK periods
---------------------------------------------------------------------------------------------------
-- Input Synchronizers --
......@@ -656,7 +663,7 @@ RSTIN_free_counter: wf_incr_counter
-- s_var_rst_c_is_full will be activated and the FSM will be reset.
free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH+2)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var_rst_c_reinit,
......@@ -669,7 +676,7 @@ free_counter: wf_incr_counter
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_c_is_seven <= '1' when s_var_rst_c = to_unsigned(7, s_var_rst_c'length) else '0';
s_var_rst_c_is_three <= '1' when s_var_rst_c = to_unsigned(3, s_var_rst_c'length) else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_four_periods -1 else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_32_periods -1 else '0';
......
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