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Mock Turtle
Commit d3151bf7 authored by Federico Vaga's avatar Federico Vaga
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doc: fix links 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 92335dd9
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README.rst
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...@@ -120,10 +120,10 @@ Mock Turtle is officially hosted on the `Open Hardware Repository`_: ...@@ -120,10 +120,10 @@ Mock Turtle is officially hosted on the `Open Hardware Repository`_:
`Mock Turtle`_. This project is distributed as a git repository which can `Mock Turtle`_. This project is distributed as a git repository which can
be cloned using the following command:: be cloned using the following command::
git clone https://@ohwr.org/gitolite/hdl-core-lib/mock-turtle.git git clone https://ohwr.org/project/mock-turtle.git
In it you can find all sources: HDL, software, demos, tests and this In it you can find all sources: HDL, software, demos, tests and this
documentation. documentation.
.. _`Open Hardware Repository`: https://www.ohwr.org/ .. _`Open Hardware Repository`: https://www.ohwr.org/
.. _`Mock Turtle`: https://www.ohwr.org/projects/mock-turtle/repository .. _`Mock Turtle`: https://www.ohwr.org/project/mock-turtle/repository
doc/architecture.rst
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...@@ -43,7 +43,7 @@ runs. Any kind of bus controller, or device must be connected externally as a ...@@ -43,7 +43,7 @@ runs. Any kind of bus controller, or device must be connected externally as a
The memory size for code and data is :ref:`configurable at synthesis time <hdl:cfg>`. The memory size for code and data is :ref:`configurable at synthesis time <hdl:cfg>`.
.. _uRV processor: https://www.ohwr.org/projects/urv-core .. _uRV processor: https://www.ohwr.org/project/urv-core
.. _`RISC-V`: https://riscv.org/ .. _`RISC-V`: https://riscv.org/
For more information about how to handle cores from software, please read: For more information about how to handle cores from software, please read:
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doc/demos/fmc-spec-carrier.rst
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...@@ -123,7 +123,7 @@ This firmware does the following things: ...@@ -123,7 +123,7 @@ This firmware does the following things:
.. highlight:: c .. highlight:: c
.. literalinclude:: ../../demos/fmc-spec-carrier/software/firmware/fw-02/fw-spec.c .. literalinclude:: ../../demos/fmc-spec-carrier/software/firmware/fw-02/fw-spec.c
.. _`FMC SPEC carrier`: https://www.ohwr.org/projects/spec/ .. _`FMC SPEC carrier`: https://www.ohwr.org/project/spec/
.. _GN4124 core: https://www.ohwr.org/projects/gn4124-core/wiki .. _GN4124 core: https://www.ohwr.org/project/gn4124-core/wiki
.. _Hdlmake: https://www.ohwr.org/projects/hdl-make/wiki .. _Hdlmake: https://www.ohwr.org/project/hdl-make/wiki
.. _OHWR general-cores: https://www.ohwr.org/projects/general-cores/wiki .. _OHWR general-cores: https://www.ohwr.org/project/general-cores/wiki
doc/demos/fmc-svec-carrier.rst
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...@@ -162,7 +162,7 @@ the possibility to play with LEDs and LEMOs status. ...@@ -162,7 +162,7 @@ the possibility to play with LEDs and LEMOs status.
.. literalinclude:: ../../demos/fmc-svec-carrier/software/tools/mockturtle-svec.c .. literalinclude:: ../../demos/fmc-svec-carrier/software/tools/mockturtle-svec.c
.. _`FMC SVEC carrier`: https://www.ohwr.org/projects/svec/ .. _`FMC SVEC carrier`: https://www.ohwr.org/project/svec/
.. _Hdlmake: https://www.ohwr.org/projects/hdl-make/wiki .. _Hdlmake: https://www.ohwr.org/project/hdl-make/wiki
.. _VME64x core: https://www.ohwr.org/projects/vme64x-core/wiki .. _VME64x core: https://www.ohwr.org/project/vme64x-core/wiki
.. _OHWR general-cores: https://www.ohwr.org/projects/general-cores/wiki .. _OHWR general-cores: https://www.ohwr.org/project/general-cores/wiki
doc/hdl/index.rst
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...@@ -472,10 +472,10 @@ The expected output from the simulation is:: ...@@ -472,10 +472,10 @@ The expected output from the simulation is::
The mock_turtle_core testbench expects an already compiled software binary under The mock_turtle_core testbench expects an already compiled software binary under
*tests/firmware/sim-verif*. Please compile the software prior to running the simulation. *tests/firmware/sim-verif*. Please compile the software prior to running the simulation.
.. _OHWR general-cores: https://www.ohwr.org/projects/general-cores/wiki .. _OHWR general-cores: https://www.ohwr.org/project/general-cores/wiki
.. _White Rabbit PTP Core: https://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core/wiki .. _White Rabbit PTP Core: https://www.ohwr.org/project/wr-cores/wiki/Wrpc_core/wiki
.. _Hdlmake: https://www.ohwr.org/projects/hdl-make/wiki .. _Hdlmake: https://www.ohwr.org/project/hdl-make/wiki
.. _uRV processor: https://www.ohwr.org/projects/urv-core/wiki .. _uRV processor: https://www.ohwr.org/project/urv-core/wiki
.. _Git submodules: https://git-scm.com/book/en/Git-Tools-Submodules .. _Git submodules: https://git-scm.com/book/en/Git-Tools-Submodules
.. highlight:: none .. highlight:: none
doc/software/index-fw.rst
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...@@ -158,7 +158,7 @@ At this point you can call ``make(1)`` to build your firmware. ...@@ -158,7 +158,7 @@ At this point you can call ``make(1)`` to build your firmware.
`soft-cpu toolchain`_ project on the `OHWR`_. `soft-cpu toolchain`_ project on the `OHWR`_.
.. _`OHWR`: https://www.ohwr.org/ .. _`OHWR`: https://www.ohwr.org/
.. _`soft-cpu toolchain`: https://www.ohwr.org/projects/soft-cpu-toolchains/wiki/wiki .. _`soft-cpu toolchain`: https://www.ohwr.org/project/soft-cpu-toolchains/wiki/wiki
.. toctree:: .. toctree::
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hdl/testbench/spec_mt_demo/synthesis_descriptor.vhd
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...@@ -5,10 +5,10 @@ ...@@ -5,10 +5,10 @@
-- Tuesday, March 13 2018 -- Tuesday, March 13 2018
-- --
-- ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores: -- ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki -- https://www.ohwr.org/project/general-cores/wiki
-- --
-- For more information on SDB meta information, see also: -- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki -- https://www.ohwr.org/project/sdb/wiki
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library ieee; library ieee;
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hdl/testbench/svec_mt_demo/synthesis_descriptor.vhd
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...@@ -5,10 +5,10 @@ ...@@ -5,10 +5,10 @@
-- Tuesday, March 13 2018 -- Tuesday, March 13 2018
-- --
-- ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores: -- ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki -- https://www.ohwr.org/project/general-cores/wiki
-- --
-- For more information on SDB meta information, see also: -- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki -- https://www.ohwr.org/project/sdb/wiki
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library ieee; library ieee;
......
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