sim: cleanup of simulation warnings and errors

bcbe024b · Dimitris Lampridis · Adam Wujek · 6f19d23b · bcbe024b · bcbe024b
Commit bcbe024b authored Apr 09, 2018 by Dimitris Lampridis Committed by Adam Wujek Apr 16, 2018
8 changed files
--- a/hdl/rtl/cpu/mt_per_cpu_csr_pkg.vhd
+++ b/hdl/rtl/cpu/mt_per_cpu_csr_pkg.vhd
@@ -30,7 +30,6 @@ package mt_per_cpu_csr_pkg is

  -- Per CPU CSR inputs (from urv to mt)
  type t_mt_per_cpu_csr_in is record
-    host_int_i       : std_logic;
    udata_i          : std_logic_vector(31 downto 0);
    dbg_cpu_status_i : std_logic;
    dbg_insn_ready_i : std_logic;

--- a/hdl/rtl/mock_turtle_core.vhd
+++ b/hdl/rtl/mock_turtle_core.vhd
@@ -383,6 +383,11 @@ begin  -- arch
    hmq_in_status(8*i + 7 downto 8*i) <= per_cb_csr_towb(i).hmqi_status_i;
    hmq_out_status(8*i + 7 downto 8*i) <= per_cb_csr_towb(i).hmqo_status_i;

+    gen_unused_rmq_slots: for j in c_CFG.rmq_config.slot_count to t_maxslot_range'high generate
+      rmq_src_o(i)(j) <= c_MT_DUMMY_SINK_IN;
+      rmq_snk_o(i)(j) <= c_MT_DUMMY_SOURCE_IN;
+    end generate gen_unused_rmq_slots;
+
    per_cb_csr_fromwb(i) <= (
      cpu_o => (
        reset_o         => cpu_csr_fromwb.reset_o(i),
@@ -403,8 +408,10 @@ begin  -- arch
    cpu_csr_towb.dbg_cpu_insn_ready_i(i) <= '0';
    cpu_csr_towb.dbg_poll_ready_i(i)     <= '0';
    cpu_csr_towb.int_i(i)                <= '0';
-    hmq_in_status(8*i + 7 downto 8*i) <= (others => '0');
-    hmq_out_status(8*i + 7 downto 8*i) <= (others => '0');
+    hmq_in_status(8*i + 7 downto 8*i)    <= (others => '0');
+    hmq_out_status(8*i + 7 downto 8*i)   <= (others => '0');
+    rmq_snk_o(i)                         <= (others => c_MT_DUMMY_SOURCE_IN);
+    rmq_src_o(i)                         <= (others => c_MT_DUMMY_SINK_IN);
  end generate gen_no_cpus;

  cpu_csr_towb.hmqi_status_lo_i <= hmq_in_status(31 downto 0);

--- a/hdl/rtl/mock_turtle_pkg.vhd
+++ b/hdl/rtl/mock_turtle_pkg.vhd
@@ -101,9 +101,9 @@ package mock_turtle_pkg is
        name      => "Mock-Turtle-Core   ")));

  type t_mt_stream_sink_in_array2d is
-    array(t_maxcpu_range) of t_mt_stream_sink_in_array(0 to 7);
+    array(t_maxcpu_range) of t_mt_stream_sink_in_array(t_maxslot_range);
  type t_mt_stream_sink_out_array2d is
-    array(t_maxcpu_range) of t_mt_stream_sink_out_array(0 to 7);
+    array(t_maxcpu_range) of t_mt_stream_sink_out_array(t_maxslot_range);

  subtype t_mt_stream_source_in_array2d is t_mt_stream_sink_out_array2d;
  subtype t_mt_stream_source_out_array2d is t_mt_stream_sink_in_array2d;

--- a/hdl/rtl/mqueue/mt_mqueue_pkg.vhd
+++ b/hdl/rtl/mqueue/mt_mqueue_pkg.vhd
@@ -70,8 +70,10 @@ package mt_mqueue_pkg is
    endpoint_id  : std_logic_vector(31 downto 0);
  end record t_mt_mqueue_slot_config;

+  subtype t_maxslot_range is natural range 0 to 7;
+
  type t_mt_mqueue_slot_config_array is
-    array(0 to 7) of t_mt_mqueue_slot_config;
+    array(t_maxslot_range) of t_mt_mqueue_slot_config;

  type t_mt_mqueue_config is record
    --  IN and OUT slots are always peered.

--- a/hdl/testbench/mock_turtle_core/.gitignore
+++ b/hdl/testbench/mock_turtle_core/.gitignore
 work/
 Makefile
 modelsim.ini
-transcript
+transcript*
 *.wlf
--- a/hdl/testbench/mock_turtle_core/main.sv
+++ b/hdl/testbench/mock_turtle_core/main.sv
@@ -40,25 +40,36 @@ module main;
      rst_n = 1;
   end

-   wire host_irq;
-
   IVHDWishboneMaster Host ( clk_sys, rst_n );

-   mock_turtle_core #
-     (
-      .g_double_core_clock(1'b0)
-      )
+   mock_turtle_core # ()
   DUT (
 	.clk_i   (clk_sys),
 	.rst_n_i (rst_n),
-	.host_slave_i (Host.master.out),
-	.host_slave_o (Host.master.in),
-	.host_irq_o(host_irq)
+	.host_slave_i (Host.out),
+	.host_slave_o (Host.in),
+	.sp_master_o (),
+	.sp_master_i (),
+	.dp_master_o (),
+	.dp_master_i (),
+	.rmq_src_o (),
+	.rmq_src_i (),
+	.rmq_snk_o (),
+	.rmq_snk_i (),
+	.clk_ref_i (),
+	.tm_i (),
+	.gpio_o (),
+	.gpio_i (),
+	.hmq_in_irq_o (),
+	.hmq_out_irq_o (),
+	.notify_irq_o (),
+	.console_irq_o ()
 	);

   initial begin
-      automatic CWishboneAccessor acc;
-      automatic MockTurtleDriver drv;
+
+      CWishboneAccessor acc;
+      MockTurtleDriver drv;

      #10us;

@@ -68,7 +79,7 @@ module main;
      drv = new(acc, 'h20000);
      drv.init();

-      drv.load_firmware(0, "../sw/hello/hello.ram.urv");
+      drv.load_firmware(0, "../sw/hello/hello.bin", 1'b0);
      drv.reset_core(0, 0);

      forever begin

--- a/hdl/testbench/mock_turtle_core/run_ci.do
+++ b/hdl/testbench/mock_turtle_core/run_ci.do
+# Modelsim run script for continuous integration
+# execute: vsim -c -do "run_ci.do"
+
+vsim -quiet -L unisim work.main
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+run 500us
+
+exit
+
--- a/hdl/testbench/svec_mt_demo/.gitignore
+++ b/hdl/testbench/svec_mt_demo/.gitignore
 work/
 Makefile
 modelsim.ini
-transcript
+transcript*
 *.wlf