rtl: remove some unused signals

96f4f0c5 · Tristan Gingold · 907f0715 · 96f4f0c5 · 96f4f0c5
Commit 96f4f0c5 authored Feb 18, 2021 by Tristan Gingold
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Showing with 1 addition and 6 deletions

mt_urv_wrapper.vhd hdl/rtl/cpu/mt_urv_wrapper.vhd +0 -3

mock_turtle_core.vhd hdl/rtl/mock_turtle_core.vhd +1 -3

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--- a/hdl/rtl/cpu/mt_urv_wrapper.vhd
+++ b/hdl/rtl/cpu/mt_urv_wrapper.vhd
@@ -91,10 +91,7 @@ architecture arch of mt_urv_wrapper is

  signal ha_im_addr     : std_logic_vector(31 downto 0);
  signal ha_im_wdata    : std_logic_vector(31 downto 0);
-  signal ha_im_rdata    : std_logic_vector(31 downto 0);
  signal ha_im_write    : std_logic;
-  signal ha_im_access   : std_logic;
-  signal ha_im_access_d : std_logic;

  signal im_addr_muxed : std_logic_vector(31 downto 0);


--- a/hdl/rtl/mock_turtle_core.vhd
+++ b/hdl/rtl/mock_turtle_core.vhd
@@ -123,6 +123,7 @@ architecture arch of mock_turtle_core is
    1 => x"00003fff",
    2 => x"0000ffff");

+  --  HAC: Host ACcess
  constant c_HAC_WISHBONE_MASTERS : integer := 4;
  constant c_HAC_MASTER_HMQ       : integer := 0;
  constant c_HAC_MASTER_CPU_CSR   : integer := 1;
@@ -175,8 +176,6 @@ architecture arch of mock_turtle_core is
  signal hmq_slave_out : t_wishbone_slave_out_array(t_cpu_range);
  signal hmq_cpu_index : natural;

-  signal hmq_in_irq_vec  : std_logic_vector(t_cpu_range);
-  signal hmq_out_irq_vec : std_logic_vector(t_cpu_range);
  signal hmq_in_irq_msk  : std_logic_vector(t_cpu_range);
  signal hmq_out_irq_msk : std_logic_vector(t_cpu_range);
  signal hmq_in_irq      : std_logic;
@@ -210,7 +209,6 @@ architecture arch of mock_turtle_core is
  signal mbx_data_towb   : t_word_array(t_maxcpu_range);
  signal dbg_insn        : t_word_array(t_maxcpu_range);
  signal dbg_insn_wr     : std_logic_vector(t_maxcpu_range);
-  signal dbg_insn_ready  : std_logic_vector(t_maxcpu_range);

  signal cpu_index : integer := 0;