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Mock Turtle
Commit 884de297 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: use updated gennum core and modified synthesis options in order to solve… 

hdl: use updated gennum core and modified synthesis options in order to solve timing problems with spec_mt_demo
parent b20a8baf
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Showing with 55 additions and 52 deletions
gn4124-core @ 6c4dca2c
Subproject commit f5b49ca3653677649c9cea0b4c94ff20c6453d43
Subproject commit 6c4dca2cad82db1064972a8f0ee7aa80aa6d5d42
hdl/syn/spec_mt_demo/syn_extra_steps.tcl
View file @ 884de297
......@@ -22,7 +22,7 @@ xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
......
hdl/top/spec_mt_demo/spec_mt_demo.vhd
View file @ 884de297
......@@ -243,56 +243,59 @@ begin -- architecture arch
cmp_gn4124_core : gn4124_core
port map (
rst_n_a_i => gn_rst_n_i,
status_o => open,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
l2p_clk_p_o => gn_l2p_clkp_o,
l2p_clk_n_o => gn_l2p_clkn_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
dma_irq_o => open,
irq_p_i => vic_master_irq,
irq_p_o => gn_gpio_b(1),
dma_reg_clk_i => clk_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
csr_clk_i => clk_sys,
csr_adr_o => gn_wbadr,
csr_dat_o => cnx_master_out(c_MASTER_PCIE).dat,
csr_sel_o => cnx_master_out(c_MASTER_PCIE).sel,
csr_stb_o => cnx_master_out(c_MASTER_PCIE).stb,
csr_we_o => cnx_master_out(c_MASTER_PCIE).we,
csr_cyc_o => cnx_master_out(c_MASTER_PCIE).cyc,
csr_dat_i => cnx_master_in(c_MASTER_PCIE).dat,
csr_ack_i => cnx_master_in(c_MASTER_PCIE).ack,
csr_stall_i => cnx_master_in(c_MASTER_PCIE).stall,
csr_err_i => cnx_master_in(c_MASTER_PCIE).err,
csr_rty_i => cnx_master_in(c_MASTER_PCIE).rty,
dma_clk_i => clk_sys,
dma_dat_i => (others => '0'),
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0');
rst_n_a_i => gn_rst_n_i,
status_o => open,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
l2p_clk_p_o => gn_l2p_clkp_o,
l2p_clk_n_o => gn_l2p_clkn_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
dma_irq_o => open,
irq_p_i => vic_master_irq,
irq_p_o => gn_gpio_b(1),
dma_reg_rst_n_i => rst_sys_n,
dma_reg_clk_i => clk_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
csr_rst_n_i => rst_sys_n,
csr_clk_i => clk_sys,
csr_adr_o => gn_wbadr,
csr_dat_o => cnx_master_out(c_MASTER_PCIE).dat,
csr_sel_o => cnx_master_out(c_MASTER_PCIE).sel,
csr_stb_o => cnx_master_out(c_MASTER_PCIE).stb,
csr_we_o => cnx_master_out(c_MASTER_PCIE).we,
csr_cyc_o => cnx_master_out(c_MASTER_PCIE).cyc,
csr_dat_i => cnx_master_in(c_MASTER_PCIE).dat,
csr_ack_i => cnx_master_in(c_MASTER_PCIE).ack,
csr_stall_i => cnx_master_in(c_MASTER_PCIE).stall,
csr_err_i => cnx_master_in(c_MASTER_PCIE).err,
csr_rty_i => cnx_master_in(c_MASTER_PCIE).rty,
dma_rst_n_i => rst_sys_n,
dma_clk_i => clk_sys,
dma_dat_i => (others => '0'),
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0');
-- drive unused GN GPIO output
gn_gpio_b(0) <= '0';
......
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