hdl: cleanup instances of chipscope

81b72665 · Dimitris Lampridis · 5c70224b · 81b72665 · 81b72665 · 81b72665
Commit 81b72665 authored Mar 16, 2018 by Dimitris Lampridis
Showing with 3 additions and 125 deletions

mock_turtle_core.vhd hdl/rtl/mock_turtle_core.vhd +1 -25

mt_rmq_incoming_slot.vhd hdl/rtl/mqueue/mt_rmq_incoming_slot.vhd +1 -57

mt_rmq_tx_path.vhd hdl/rtl/mqueue/mt_rmq_tx_path.vhd +1 -43

No files found.
--- a/hdl/rtl/mock_turtle_core.vhd
+++ b/hdl/rtl/mock_turtle_core.vhd
@@ -177,21 +177,6 @@ architecture rtl of mock_turtle_core is
      master_o : out t_wishbone_master_out);
  end component mt_wb_remapper;
-  component chipscope_ila
-    port (
-      CONTROL : inout std_logic_vector(35 downto 0);
-      CLK     : in    std_logic;
-      TRIG0   : in    std_logic_vector(31 downto 0);
-      TRIG1   : in    std_logic_vector(31 downto 0);
-      TRIG2   : in    std_logic_vector(31 downto 0);
-      TRIG3   : in    std_logic_vector(31 downto 0));
-  end component;
-  component chipscope_icon
-    port (
-      CONTROL0 : inout std_logic_vector (35 downto 0));
-  end component;
  ------------------------------------------
  --        CONSTANTS DECLARATION
  ------------------------------------------
@@ -325,15 +310,6 @@ architecture rtl of mock_turtle_core is
  signal cpu_pcs_valid : std_logic_vector(t_cpu_rng);
  signal cpu_pcs       : t_pc_array(0 to g_config.cpu_count-1);
-  --  Signals for chip Scope  -----------------
-  signal CONTROL    : std_logic_vector(35 downto 0);
-  signal CLK        : std_logic;
-  signal TRIG0      : std_logic_vector(31 downto 0);
-  signal TRIG1      : std_logic_vector(31 downto 0);
-  signal TRIG2      : std_logic_vector(31 downto 0);
-  signal TRIG3      : std_logic_vector(31 downto 0);
-  ---------------------------------------------
  ------------------------------------------
  --        FUNCTIONS DECLARATION
  ------------------------------------------
@@ -582,7 +558,7 @@ begin  -- rtl
        wr_snk_o     => wr_snk_o,
        wr_snk_i     => wr_snk_i,
        rmq_status_o => rmq_status,
-        debug_o      => trig2);
+        debug_o      => open);
  end generate gen_with_rmq;

--- a/hdl/rtl/mqueue/mt_rmq_incoming_slot.vhd
+++ b/hdl/rtl/mqueue/mt_rmq_incoming_slot.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2014-04-01
-- Last update: 2017-05-15
+-- Last update: 2018-03-16
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -127,29 +127,6 @@ architecture rtl of mt_rmq_incoming_slot is
  constant c_addr_dst_type2  : integer := 10;
  constant c_addr_dst_type3  : integer := 11;
-  component chipscope_ila
-    port (
-      CONTROL : inout std_logic_vector(35 downto 0);
-      CLK     : in    std_logic;
-      TRIG0   : in    std_logic_vector(31 downto 0);
-      TRIG1   : in    std_logic_vector(31 downto 0);
-      TRIG2   : in    std_logic_vector(31 downto 0);
-      TRIG3   : in    std_logic_vector(31 downto 0));
-  end component;
-  component chipscope_icon
-    port (
-      CONTROL0 : inout std_logic_vector (35 downto 0));
-  end component;
-  signal CONTROL : std_logic_vector(35 downto 0);
-  signal CLK     : std_logic;
-  signal TRIG0   : std_logic_vector(31 downto 0);
-  signal TRIG1   : std_logic_vector(31 downto 0);
-  signal TRIG2   : std_logic_vector(31 downto 0);
-  signal TRIG3   : std_logic_vector(31 downto 0);
  signal config : t_rmq_incoming_slot_config;
  signal match_type0, match_type1, match_type2, match_type3, match_dst_mac, match_dst_ip, match_udp, match_ethertype, match_dst_port, match_raw, match : std_logic;
@@ -545,38 +522,5 @@ begin  -- rtl
  stat_o.full  <= full;
  stat_o.empty <= empty;
  stat_o.count <= std_logic_vector(occupied);
-gen_cc : if (g_id = 0) generate
-  chipscope_ila_1 : chipscope_ila
-    port map (
-      CONTROL => CONTROL,
-      CLK     => clk_i,
-      TRIG0   => TRIG0,
-      TRIG1   => TRIG1,
-      TRIG2   => TRIG2,
-      TRIG3   => TRIG3);
-  trig0(0) <= snk_i.valid;
-  trig0(1) <= snk_i.last;
-  trig0(2) <= empty;
-  trig0(3) <= full;
-  trig0(4) <= outb_i.sel;
-  trig0(6) <= outb_i.we;
-  trig0(5) <= mem_we;
-  trig0(15 downto 12) <= std_logic_vector(to_unsigned(t_wr_state'pos(wr_state), 4));
-  trig0(11 downto 8) <= std_logic_vector(to_unsigned(t_rd_state'pos(rd_state), 4));
-  trig0(31 downto 16) <= snk_i.data(15 downto 0);
-  trig1(9 downto 0)   <= outb_i.adr;
-  trig2               <= outb_out.dat;
-  chipscope_icon_1 : chipscope_icon
-    port map (
-      CONTROL0 => CONTROL);
-  end generate gen_cc;
 end rtl;
--- a/hdl/rtl/mqueue/mt_rmq_tx_path.vhd
+++ b/hdl/rtl/mqueue/mt_rmq_tx_path.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2014-04-01
-- Last update: 2018-02-26
+-- Last update: 2018-03-16
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -76,28 +76,6 @@ architecture rtl of mt_rmq_tx_path is
  signal fwd_pipe : t_mt_stream_source_out_array(0 to 2);
  signal rev_pipe : t_mt_stream_source_in_array(0 to 2);
-    component chipscope_ila
-    port (
-      CONTROL : inout std_logic_vector(35 downto 0);
-      CLK     : in    std_logic;
-      TRIG0   : in    std_logic_vector(31 downto 0);
-      TRIG1   : in    std_logic_vector(31 downto 0);
-      TRIG2   : in    std_logic_vector(31 downto 0);
-      TRIG3   : in    std_logic_vector(31 downto 0));
-  end component;
-  component chipscope_icon
-    port (
-      CONTROL0 : inout std_logic_vector (35 downto 0));
-  end component;
-  signal CONTROL : std_logic_vector(35 downto 0);
-  signal CLK     : std_logic;
-  signal TRIG0   : std_logic_vector(31 downto 0);
-  signal TRIG1   : std_logic_vector(31 downto 0);
-  signal TRIG2   : std_logic_vector(31 downto 0);
-  signal TRIG3   : std_logic_vector(31 downto 0);
 signal p_payload_len : std_logic_vector(15 downto 0);
  component mt_rmq_tx_packer is
@@ -178,26 +156,6 @@ p_payload_len <= std_logic_vector(unsigned(p_payload_words_i) sll 1);
      p_dst_mac_i   => p_dst_mac_i,
      p_ethertype_i => p_ethertype_i);
-    chipscope_ila_1 : chipscope_ila
-      port map (
-        CONTROL => CONTROL,
-        CLK     => clk_i,
-        TRIG0   => TRIG0,
-        TRIG1   => TRIG1,
-        TRIG2   => TRIG2,
-        TRIG3   => TRIG3);
-    chipscope_icon_1 : chipscope_icon
-      port map (
-        CONTROL0 => CONTROL);
-trig0(0)  <= fwd_pipe(2).valid;
-trig0(1)  <= fwd_pipe(2).last;
-trig0(17 downto 2) <= fwd_pipe(2).data(15 downto 0);
-trig0(19 downto 18) <= fwd_pipe(2).tag(1 downto 0);
-trig0(20) <= rev_pipe(2).ready;
  src_o       <= fwd_pipe(2);
  rev_pipe(2) <= src_i;