hdl: add attributes to help with declaring timing constraints

5ce1aa6d · Dimitris Lampridis · 27e6198c · 5ce1aa6d
Commit 5ce1aa6d authored Jul 27, 2018 by Dimitris Lampridis
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Showing with 7 additions and 2 deletions

mt_cpu_cb.vhd hdl/rtl/cpu/mt_cpu_cb.vhd +7 -2

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--- a/hdl/rtl/cpu/mt_cpu_cb.vhd
+++ b/hdl/rtl/cpu/mt_cpu_cb.vhd
@@ -133,6 +133,11 @@ architecture arch of mt_cpu_cb is
  alias a_hmq_config : t_mt_mqueue_config is g_CPU_CONFIG.hmq_config;

  constant c_HMQ_COUNT : natural := a_hmq_config.slot_count;
+
+  -- necessary to relax timing on p_tm_cross process
+  attribute keep : string;
+  attribute keep of tm_p_sys : signal is "true";
+
 begin  -- arch

  gen_with_wr_1 : if g_WITH_WHITE_RABBIT generate
@@ -184,7 +189,7 @@ begin  -- arch
      end if;
    end process;

-    process(clk_sys_i)
+    p_tm_cross: process(clk_sys_i)
    begin
      if rising_edge(clk_sys_i) then
        if tm_p_sys = '1' then
@@ -193,7 +198,7 @@ begin  -- arch
        end if;
        cycles_sys_d0 <= cycles_sys;
      end if;
-    end process;
+    end process p_tm_cross;

    -- ugly hack!
    process(clk_sys_i)