hdl: disable show-ahead legacy mode for UART fifo

With this flag, the full UART FIFO will be used and the 'full' flag will be properly raised. See also the relevant comments in the general-cores module.

hdl: disable show-ahead legacy mode for UART fifo
With this flag, the full UART FIFO will be used and the 'full' flag will be properly raised. See also the relevant comments in the general-cores module.
26e99818 · Dimitris Lampridis · 7e10d2db · 26e99818
Commit 26e99818 authored Jan 05, 2023 by Dimitris Lampridis
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mt_cpu_cb.vhd hdl/rtl/cpu/mt_cpu_cb.vhd +5 -5

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--- a/hdl/rtl/cpu/mt_cpu_cb.vhd
+++ b/hdl/rtl/cpu/mt_cpu_cb.vhd
@@ -410,11 +410,11 @@ begin  -- arch

  U_Uart_Message_FIFO : generic_sync_fifo
    generic map (
-      g_DATA_WIDTH => 8,
-      g_SIZE       => c_MT_UART_MESSAGE_FIFO_SIZE,
-      g_SHOW_AHEAD => TRUE,
-      g_WITH_COUNT => TRUE)
-
+      g_DATA_WIDTH             => 8,
+      g_SIZE                   => c_MT_UART_MESSAGE_FIFO_SIZE,
+      g_SHOW_AHEAD_LEGACY_MODE => FALSE,
+      g_SHOW_AHEAD             => TRUE,
+      g_WITH_COUNT             => TRUE)
    port map (
      rst_n_i => uart_fifo_reset_n,
      clk_i   => clk_sys_i,