hdl: wrong slot indexing in mqueue wishbone slave

Currently, the way we choose a specific slot and direction in a message queue is based solely on the wishbone address:

 slot_num     <= slave_i.adr(18 downto 16);
 in_area_sel  <= '1' when slave_i.adr(15) = '0' else '0';
 out_area_sel <= '1' when slave_i.adr(15) = '1' else '0';

This causes an issue because in case of a multi-cpu system, where this adress will reach the HMQ of all CPUs and will cause all CPUs to select that particular slot and direction, even if wishbone cycle is not asserted.

Therefore this breaks all multi-cpu testbenches with assymetric HMQ slots, because an index that exists in one HMQ might not exist in another one. It might also cause data corruption and unexpected behavior if a message is indeed delivered in multiple HMQs.