... | ... | @@ -6,7 +6,7 @@ the following table: |
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|**Work Package**|**Description**|**Status**|
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|[WP1](WP1)|**Scope, objectives, resources, budget** definition; evaluation of the **Strukton solution**|[Done](https://www.ohwr.org/project/masterfip/uploads/d2e6fadb19f962b82f93972daf1f06b8/masterFIP_technical_choice.pdf)|
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|[WP1](WP1)|**Scope, objectives, resources, budget** definition; evaluation of the **Strukton solution**|[Done](https://ohwr.org/project/masterfip/uploads/d2e6fadb19f962b82f93972daf1f06b8/masterFIP_technical_choice.pdf)|
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|[WP2](WP2)|**Functional specification** drafting|[Done](https://www.ohwr.org//edms.cern.ch/ui/#!master/navigator/document?d:1938176066:1938176066:subdocs)|
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|[WP3](WP3)|**Gateware**: writing of VHDL code or extending Strukton code|[Done](https://www.ohwr.org/project/masterfip-gw/wiki)|
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|[WP4](WP4)|**Gateware testing**: VHDL Testbench|[Done](https://ohwr.org/project/masterfip-gw/tree/tom-systemverilog-testbench)|
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... | ... | |