Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
M
MasterFIP - Testing
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
MasterFIP - Testing
Commits
8837f242
Commit
8837f242
authored
Jul 26, 2016
by
Marek Gumiński
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Added units to ADC plots
parent
1b25c761
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
15 additions
and
3 deletions
+15
-3
test03.py
python/test03.py
+15
-3
No files found.
python/test03.py
View file @
8837f242
...
...
@@ -273,9 +273,21 @@ def test_transmission( dut, transmission, should_succed = True, primary = True )
else
:
result
[
'Captured ADC transmission'
]
=
1
plt
.
plot
(
diff
)
plt
.
ylabel
(
"Signal [LSB]"
)
plt
.
xlabel
(
"Time [samples]"
)
# ADC sampling freq is constant, but undersampling is changed depending on bus speed
# result sampling frequency is lower
# 1e6 to get [us]
sampleperiod
=
1e6
/
(
dut
.
adc_sampling_freq
/
customconf
.
undersampling
)
# create time vector
xxrange
=
numpy
.
linspace
(
0
,
sampleperiod
*
len
(
diff
),
len
(
diff
))
# make plot
plt
.
plot
(
xxrange
,
1000.0
*
diff
/
2.0
**
16
)
#make is look good
plt
.
title
(
"Differential WordFIP signal (ADC CH1-CH2)"
)
plt
.
ylabel
(
"Signal [mV]"
)
plt
.
xlabel
(
"Time [us]"
)
plt
.
savefig
(
"/tmp/image.png"
)
plt
.
close
()
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment