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MasterFIP - Gateware
Commit f281ca50 authored by Matthieu Cattin's avatar Matthieu Cattin
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doc: Add new ohr logo, alternative gateware arch

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doc/figures/masterfip_gw_arch.svg
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doc/figures/ohr_logo.svg 0 → 100644
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doc/tech_spec/masterFIP_technical_specification.in
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......@@ -44,7 +44,9 @@
@subtitle @value{update-month}
@subtitle Includes gateware and firmware specification
@sp 10
@center @image{../figures/cern_logo,3cm,,,pdf} @hfill @image{../figures/ohr_logo,3cm,,,pdf}
@multitable @columnfractions .5 .5
@item @image{../figures/cern_logo,3cm,,,pdf} @tab @image{../figures/ohr_logo,3cm,,,pdf}
@end multitable
@author Matthieu Cattin (CERN)
@end titlepage
@headings single
......@@ -57,6 +59,7 @@
@node Top
@top Introduction
Uses wr-node core.
@c ##########################################################################
......@@ -68,15 +71,43 @@
@section Build from Sources
@c ##########################################################################
@page
@node Host interface
@chapter Host interface
@c ==========================================================================
@section Host message queue (HMQ)
@ignore
@table @b
@item HMQ slot 0
general control and status
in/out
@item HMQ slot 1
produced variables
in
@item HMQ slot 2
consumed variables
out
@item HMQ slot 3
produced messages
in
@item HMQ slot 4
comsumed messages
out
@end table
@ignore
The fmc-adc hdl design make use of the @command{hdlmake}@footnote{@uref{http://www.ohwr.org/projects/hdl-make}} tool.
It automatically fetches the required hdl cores and libraries. It also generates Makefiles for synthesis/par and simulation.
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