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MasterFIP - Gateware
Commits
e1f798ee
Commit
e1f798ee
authored
Nov 10, 2015
by
Evangelia Gousiou
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masterFIP_core and wr_node_core at 100MHz instead of 40MHz
parent
4877b599
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10 changed files
with
276 additions
and
194 deletions
+276
-194
wf_package.vhd
rtl/from_nanofip/wf_package.vhd
+2
-2
masterFIP_pkg.vhd
rtl/masterFIP_pkg.vhd
+0
-6
masterFIP_test.vec
sim/spec/data_vectors/masterFIP_test.vec
+76
-16
user_logic_config.txt
sim/spec/data_vectors/user_logic_config.txt
+2
-2
tb_masterFIP.vhd
sim/spec/testbench/tb_masterFIP.vhd
+3
-3
spec_masterfip_wrnode.xise
syn/spec_wrnode/spec_masterfip_wrnode.xise
+84
-45
spec_masterFIP.ucf
top/spec/spec_masterFIP.ucf
+0
-6
spec_masterFIP.vhd
top/spec/spec_masterFIP.vhd
+8
-12
spec_top.ucf
top/spec_wrnode/spec_top.ucf
+7
-1
spec_top.vhd
top/spec_wrnode/spec_top.vhd
+94
-101
No files found.
rtl/from_nanofip/wf_package.vhd
View file @
e1f798ee
...
@@ -66,7 +66,7 @@ package wf_package is
...
@@ -66,7 +66,7 @@ package wf_package is
-- Constant regarding the user clock --
-- Constant regarding the user clock --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
constant
c_QUARTZ_PERIOD
:
real
:
=
25
.
0
;
constant
c_QUARTZ_PERIOD
:
real
:
=
10
.
0
;
----------***-----25
...
@@ -267,7 +267,7 @@ package wf_package is
...
@@ -267,7 +267,7 @@ package wf_package is
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant
c_PERIODS_COUNTER_LGTH
:
natural
:
=
1
1
;
-- in the slowest bit rate (31.25kbps), the
constant
c_PERIODS_COUNTER_LGTH
:
natural
:
=
1
3
;
-- in the slowest bit rate (31.25kbps), the -------***---------- 11
-- period is 32000 ns and can be measured after
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- bits is the max needed for counting
...
...
rtl/masterFIP_pkg.vhd
View file @
e1f798ee
...
@@ -135,12 +135,6 @@ package masterFIP_pkg is
...
@@ -135,12 +135,6 @@ package masterFIP_pkg is
name
=>
"WB-MASTERFIP.CSR "
)));
name
=>
"WB-MASTERFIP.CSR "
)));
---------------------------------------------------------------------------------------------------
-- Constant regarding the user clock --
---------------------------------------------------------------------------------------------------
constant
c_QUARTZ_PERIOD
:
real
:
=
25
.
0
;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Vector with the data Registers --
-- Vector with the data Registers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
...
...
sim/spec/data_vectors/masterFIP_test.vec
View file @
e1f798ee
...
@@ -44,15 +44,16 @@ wait %d20
...
@@ -44,15 +44,16 @@ wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
-- macrocycle cnt start
--wr 0000000000030018 F 80001D00
wr 000000000003001C F 80004880
--wait %d20
wait %d20
--wr 000000000003001C F 00002A6D
-- turnar counter top
-- turnar counter top
--wr 00000000000300
1C
F 000007D0
--wr 00000000000300
20
F 000007D0
--wait %d20
--wait %d20
-- silen counter top
-- silen counter top
--wr 000000000003002
0
F 00000FA0
--wr 000000000003002
4
F 00000FA0
--wait %d20
--wait %d20
...
@@ -92,16 +93,9 @@ wait %d20
...
@@ -92,16 +93,9 @@ wait %d20
wr 0000000000030158 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wr 0000000000030158 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wait %d20
wr 000000000003015c F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wr 000000000003015c F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wait %d20
wr 0000000000030160 F 0A05A2A1
wait %d20
wr 0000000000030164 F 0E0D0C0B
wait %d20
wr 0000000000030168 F 06060605
wait %d20
-- tx_start
-- tx_start
wr 0000000000030034 F 00000502 -- for 2 data bytes: 0
502 | for 8 data bytes:
0B02
wr 0000000000030034 F 00000502 -- for 2 data bytes: 0
0000502 | for 8 data bytes: 0000
0B02
wait %d40000
wait %d40000
...
@@ -165,13 +159,79 @@ wait %d40000
...
@@ -165,13 +159,79 @@ wait %d40000
-- read received data
-- read received data
rd 0000000000030048 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
rd 0000000000030048 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d
40
0
wait %d
2
0
rd 000000000003004c F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
rd 000000000003004c F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d
40
0
wait %d
2
0
rd 0000000000030050 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
rd 0000000000030050 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d
40
0
wait %d
2
0
rd 0000000000030054 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000030054 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d400
wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003005C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030070 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030074 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030078 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003007C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030080 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030084 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030088 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003008C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030090 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030094 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030098 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003009C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300AC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300BC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300CC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300DC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
wait %d40000
wait %d40000
--------------- RP_FIN ---------------
--------------- RP_FIN ---------------
...
...
sim/spec/data_vectors/user_logic_config.txt
View file @
e1f798ee
25
ns -- User clock period (should not be modified during test)
10
ns -- User clock period (should not be modified during test)
25
ns -- Wishbone interface clock period (should not be modified during test)
10
ns -- Wishbone interface clock period (should not be modified during test)
3 us -- Power-on reset length
3 us -- Power-on reset length
1 us -- User reset length
1 us -- User reset length
1 us -- Wishbone interface reset length
1 us -- Wishbone interface reset length
...
...
sim/spec/testbench/tb_masterFIP.vhd
View file @
e1f798ee
...
@@ -728,9 +728,9 @@ begin
...
@@ -728,9 +728,9 @@ begin
-- wait for nanoFIP_clk_period/2;
-- wait for nanoFIP_clk_period/2;
-- end process;
-- end process;
--
ext_sync <= '1' after 8500 ns, '0' after 8580 ns,
ext_sync
<=
'1'
after
8500
ns
,
'0'
after
8580
ns
,
--
'1' after 194000 ns, '0' after 194080 ns,
'1'
after
194000
ns
,
'0'
after
194080
ns
,
--
'1' after 565151 ns, '0' after 565231 ns;
'1'
after
565151
ns
,
'0'
after
565231
ns
;
rst_n
<=
RSTOUT18n
;
rst_n
<=
RSTOUT18n
;
GPIO
(
0
)
<=
irq_p
;
GPIO
(
0
)
<=
irq_p
;
...
...
syn/spec_wrnode/spec_masterfip_wrnode.xise
View file @
e1f798ee
This diff is collapsed.
Click to expand it.
top/spec/spec_masterFIP.ucf
View file @
e1f798ee
...
@@ -67,12 +67,6 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
...
@@ -67,12 +67,6 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_n_o" LOC = W10;
NET "led_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "led_out_of_sync_n_o" LOC = Y10;
NET "led_out_of_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
...
...
top/spec/spec_masterFIP.vhd
View file @
e1f798ee
...
@@ -178,8 +178,6 @@ entity spec_masterFIP is
...
@@ -178,8 +178,6 @@ entity spec_masterFIP is
led_tx_act_n_o
:
out
std_logic
;
led_tx_act_n_o
:
out
std_logic
;
led_rx_err_n_o
:
out
std_logic
;
led_rx_err_n_o
:
out
std_logic
;
led_rx_act_n_o
:
out
std_logic
;
led_rx_act_n_o
:
out
std_logic
;
led_out_of_sync_n_o
:
out
std_logic
;
led_sync_n_o
:
out
std_logic
;
-- LEDs spec
-- LEDs spec
led_green_o
:
out
std_logic
;
led_green_o
:
out
std_logic
;
...
@@ -232,7 +230,7 @@ architecture rtl of spec_masterFIP is
...
@@ -232,7 +230,7 @@ architecture rtl of spec_masterFIP is
signal
clk_40m_sys
,
rst_sys
:
std_logic
;
signal
clk_40m_sys
,
rst_sys
:
std_logic
;
signal
rst_sys_n
:
std_logic
;
signal
rst_sys_n
:
std_logic
;
signal
pllout_clk_sys
,
pllout_clk_sys_fb
:
std_logic
;
signal
pllout_clk_sys
,
pllout_clk_sys_fb
:
std_logic
;
signal
sys_locked
:
std_logic
;
signal
sys_locked
,
pll_status
:
std_logic
;
-- WISHBONE from crossbar master port
-- WISHBONE from crossbar master port
signal
cnx_master_out
:
t_wishbone_master_out_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
signal
cnx_master_out
:
t_wishbone_master_out_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
signal
cnx_master_in
:
t_wishbone_master_in_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
signal
cnx_master_in
:
t_wishbone_master_in_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
...
@@ -245,7 +243,7 @@ architecture rtl of spec_masterFIP is
...
@@ -245,7 +243,7 @@ architecture rtl of spec_masterFIP is
-- Carrier 1-wire
-- Carrier 1-wire
signal
carrier_owr_en
,
carrier_owr_i
:
std_logic_vector
(
c_FMC_ONEWIRE_NB
-
1
downto
0
);
signal
carrier_owr_en
,
carrier_owr_i
:
std_logic_vector
(
c_FMC_ONEWIRE_NB
-
1
downto
0
);
-- VIC
-- VIC
signal
fmc_eic_irq
:
std_logic
;
signal
fmc_eic_irq
,
irq_to_gn4124
:
std_logic
;
signal
fmc_eic_irq_synch
:
std_logic_vector
(
1
downto
0
);
signal
fmc_eic_irq_synch
:
std_logic_vector
(
1
downto
0
);
-- EEPROM on mezzanine
-- EEPROM on mezzanine
signal
tdc_scl_out
,
tdc_scl_in
,
tdc_sda_out
,
tdc_sda_in
:
std_logic
;
signal
tdc_scl_out
,
tdc_scl_in
,
tdc_sda_out
,
tdc_sda_in
:
std_logic
;
...
@@ -283,10 +281,10 @@ begin
...
@@ -283,10 +281,10 @@ begin
DIVCLK_DIVIDE
=>
1
,
DIVCLK_DIVIDE
=>
1
,
CLKFBOUT_MULT
=>
50
,
CLKFBOUT_MULT
=>
50
,
CLKFBOUT_PHASE
=>
0
.
000
,
CLKFBOUT_PHASE
=>
0
.
000
,
CLKOUT0_DIVIDE
=>
25
,
-- 40 MHz
CLKOUT0_DIVIDE
=>
10
,
-- 40 MHz ----***---- 25 10
CLKOUT0_PHASE
=>
0
.
000
,
CLKOUT0_PHASE
=>
0
.
000
,
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT1_DIVIDE
=>
8
,
-- 125 MHz, not used
CLKOUT1_DIVIDE
=>
8
,
-- 125 MHz, not used
CLKOUT1_PHASE
=>
0
.
000
,
CLKOUT1_PHASE
=>
0
.
000
,
CLKOUT1_DUTY_CYCLE
=>
0
.
500
,
CLKOUT1_DUTY_CYCLE
=>
0
.
500
,
CLKOUT2_DIVIDE
=>
16
,
CLKOUT2_DIVIDE
=>
16
,
...
@@ -314,7 +312,7 @@ begin
...
@@ -314,7 +312,7 @@ begin
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Reset for
40
MHz clk domain --
-- Reset for
62.5
MHz clk domain --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
cmp_spec_rst_gen
:
spec_reset_gen
cmp_spec_rst_gen
:
spec_reset_gen
...
@@ -387,7 +385,7 @@ begin
...
@@ -387,7 +385,7 @@ begin
vc_rdy_i
=>
vc_rdy_i
,
vc_rdy_i
=>
vc_rdy_i
,
-- Interrupt interface
-- Interrupt interface
dma_irq_o
=>
open
,
dma_irq_o
=>
open
,
irq_p_i
=>
'0'
,
irq_p_i
=>
irq_to_gn4124
,
irq_p_o
=>
irq_p_o
,
irq_p_o
=>
irq_p_o
,
-- CSR WISHBONE interface (master pipelined)
-- CSR WISHBONE interface (master pipelined)
csr_clk_i
=>
clk_40m_sys
,
csr_clk_i
=>
clk_40m_sys
,
...
@@ -513,11 +511,9 @@ begin
...
@@ -513,11 +511,9 @@ begin
-- extended_o => rx_act);
-- extended_o => rx_act);
led_tx_err_n_o
<=
aux
(
5
);
led_tx_err_n_o
<=
aux
(
5
);
led_tx_act_n_o
<=
aux
(
3
);
led_tx_act_n_o
<=
aux
(
0
);
led_rx_err_n_o
<=
aux
(
2
);
led_rx_err_n_o
<=
aux
(
2
);
led_rx_act_n_o
<=
aux
(
6
);
led_rx_act_n_o
<=
aux
(
6
);
led_out_of_sync_n_o
<=
aux
(
7
);
led_sync_n_o
<=
aux
(
0
);
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
...
@@ -566,7 +562,7 @@ begin
...
@@ -566,7 +562,7 @@ begin
carrier_info_carrier_type_i
=>
c_CARRIER_TYPE
,
carrier_info_carrier_type_i
=>
c_CARRIER_TYPE
,
carrier_info_stat_fmc_pres_i
=>
prsnt_m2c_n_i
,
carrier_info_stat_fmc_pres_i
=>
prsnt_m2c_n_i
,
carrier_info_stat_p2l_pll_lck_i
=>
gn4124_status
(
0
),
carrier_info_stat_p2l_pll_lck_i
=>
gn4124_status
(
0
),
carrier_info_stat_sys_pll_lck_i
=>
'0'
,
carrier_info_stat_sys_pll_lck_i
=>
pll_status
,
carrier_info_stat_ddr3_cal_done_i
=>
'0'
,
carrier_info_stat_ddr3_cal_done_i
=>
'0'
,
carrier_info_stat_reserved_i
=>
(
others
=>
'0'
),
carrier_info_stat_reserved_i
=>
(
others
=>
'0'
),
carrier_info_ctrl_led_green_o
=>
open
,
carrier_info_ctrl_led_green_o
=>
open
,
...
...
top/spec_wrnode/spec_top.ucf
View file @
e1f798ee
...
@@ -225,7 +225,7 @@ NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
...
@@ -225,7 +225,7 @@ NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R
9
;
NET "adc_5v_en_n_o" LOC = R
8
;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
...
@@ -245,6 +245,12 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
...
@@ -245,6 +245,12 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_n_o" LOC = W10;
NET "led_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "led_out_of_sync_n_o" LOC = Y10;
NET "led_out_of_sync_n_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
...
...
top/spec_wrnode/spec_top.vhd
View file @
e1f798ee
...
@@ -59,103 +59,94 @@ library unisim;
...
@@ -59,103 +59,94 @@ library unisim;
use
unisim
.
vcomponents
.
all
;
use
unisim
.
vcomponents
.
all
;
entity
spec_top
is
entity
spec_top
is
generic
(
generic
(
g_simulation
:
boolean
:
=
false
);
g_simulation
:
boolean
:
=
false
);
port
(
-- Clocks
port
(
clk_20m_vcxo_i
:
in
std_logic
;
-- 20MHz VCXO
clk_125m_pllref_p_i
:
in
std_logic
;
-- 125 MHz PLL reference
clk_125m_pllref_n_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
;
-- 20MHz VCXO clock
clk_125m_gtp_n_i
:
in
std_logic
;
-- 125 MHz GTP reference
clk_125m_gtp_p_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
-- 125 MHz PLL reference
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
-- 125 MHz GTP reference
clk_125m_gtp_p_i
:
in
std_logic
;
L_RST_N
:
in
std_logic
;
-- Gennum Local bus reset
-- general purpose interface
gpio
:
inout
std_logic_vector
(
1
downto
0
);
-- gpio[0] -> gn4124 gpio8
-- gpio[1] -> gn4124 gpio9
-- pcie to local [inbound data] - rx
p2l_rdy
:
out
std_logic
;
-- rx buffer full flag
p2l_clkn
:
in
std_logic
;
-- receiver source synchronous clock-
p2l_clkp
:
in
std_logic
;
-- receiver source synchronous clock+
p2l_data
:
in
std_logic_vector
(
15
downto
0
);
-- parallel receive data
p2l_dframe
:
in
std_logic
;
-- receive frame
p2l_valid
:
in
std_logic
;
-- receive data valid
-- inbound buffer request/status
p_wr_req
:
in
std_logic_vector
(
1
downto
0
);
-- pcie write request
p_wr_rdy
:
out
std_logic_vector
(
1
downto
0
);
-- pcie write ready
rx_error
:
out
std_logic
;
-- receive error
-- local to parallel [outbound data] - tx
l2p_data
:
out
std_logic_vector
(
15
downto
0
);
-- parallel transmit data
l2p_dframe
:
out
std_logic
;
-- transmit data frame
l2p_valid
:
out
std_logic
;
-- transmit data valid
l2p_clkn
:
out
std_logic
;
-- transmitter source synchronous clock-
l2p_clkp
:
out
std_logic
;
-- transmitter source synchronous clock+
l2p_edb
:
out
std_logic
;
-- packet termination and discard
-- outbound buffer status
l2p_rdy
:
in
std_logic
;
-- tx buffer full flag
l_wr_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- local-to-pcie write
p_rd_d_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- pcie-to-local read response data ready
tx_error
:
in
std_logic
;
-- transmit error
vc_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- channel ready
-- front panel leds
led_red
:
out
std_logic
;
led_green
:
out
std_logic
;
fmc_scl_b
:
inout
std_logic
;
-- SPEC EEPROM (on
-- the mezz)
fmc_sda_b
:
inout
std_logic
;
carrier_onewire_b
:
inout
std_logic
;
-- SPEC 1-wire
fmc_prsnt_m2c_l_i
:
in
std_logic
;
-- Bus Speed
speed_b0_i
:
in
std_logic
;
speed_b1_i
:
in
std_logic
;
-- Bus termination
bus_term_en_n_o
:
out
std_logic
;
-- 150 Ohms termination of the bus -- check again
-- External synchronisation pulse transceiver
-- GENNUM interface
ext_sync_term_en_o
:
out
std_logic
;
-- enable 50 Ohms termination of the pulse
L_RST_N
:
in
std_logic
;
-- local bus reset
ext_sync_dir_o
:
out
std_logic
;
-- transceiver direction
gpio
:
inout
std_logic_vector
(
1
downto
0
);
-- general purpose interface
ext_sync_oe_o
:
out
std_logic
;
-- transceiver output enable
p2l_rdy
:
out
std_logic
;
-- pcie to local [inbound data] - rx
ext_sync_tst_n_o
:
out
std_logic
;
-- emulation of the LEMO input
p2l_clkn
:
in
std_logic
;
ext_sync_i
:
in
std_logic
;
-- sync pulse
p2l_clkp
:
in
std_logic
;
p2l_data
:
in
std_logic_vector
(
15
downto
0
);
p2l_dframe
:
in
std_logic
;
p2l_valid
:
in
std_logic
;
p_wr_req
:
in
std_logic_vector
(
1
downto
0
);
-- inbound buffer request/status
p_wr_rdy
:
out
std_logic_vector
(
1
downto
0
);
rx_error
:
out
std_logic
;
l2p_data
:
out
std_logic_vector
(
15
downto
0
);
-- local to parallel [outbound data] - tx
l2p_dframe
:
out
std_logic
;
l2p_valid
:
out
std_logic
;
l2p_clkn
:
out
std_logic
;
l2p_clkp
:
out
std_logic
;
l2p_edb
:
out
std_logic
;
l2p_rdy
:
in
std_logic
;
-- outbound buffer status
l_wr_rdy
:
in
std_logic_vector
(
1
downto
0
);
p_rd_d_rdy
:
in
std_logic_vector
(
1
downto
0
);
tx_error
:
in
std_logic
;
vc_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- SPEC LEDs
led_red
:
out
std_logic
;
led_green
:
out
std_logic
;
-- SPEC EEPROM
fmc_scl_b
:
inout
std_logic
;
fmc_sda_b
:
inout
std_logic
;
-- Power supplies for the ADC
-- SPEC 1-wire
adc_1v8_shdn_n_o
:
out
std_logic
;
carrier_onewire_b
:
inout
std_logic
;
adc_m5v_shdn_n_o
:
out
std_logic
;
fmc_prsnt_m2c_l_i
:
in
std_logic
;
adc_5v_en_n_o
:
out
std_logic
;
-- WorldFIP bus speed
-- FielDrive
speed_b0_i
:
in
std_logic
;
fd_rxcdn_i
:
in
std_logic
;
speed_b1_i
:
in
std_logic
;
fd_rxd_i
:
in
std_logic
;
fd_txer_i
:
in
std_logic
;
-- WorldFIP bus termination
fd_wdgn_i
:
in
std_logic
;
bus_term_en_n_o
:
out
std_logic
;
-- 150 Ohms termination of the bus -- check again
fd_rstn_o
:
out
std_logic
;
fd_txck_o
:
out
std_logic
;
-- WorldFIP external synchronisation pulse transceiver
fd_txd_o
:
out
std_logic
;
ext_sync_term_en_o
:
out
std_logic
;
-- enable 50 Ohms termination of the pulse
fd_txena_o
:
out
std_logic
;
ext_sync_dir_o
:
out
std_logic
;
-- transceiver direction
ext_sync_oe_o
:
out
std_logic
;
-- transceiver output enable
-- LEDs mezzanine
ext_sync_tst_n_o
:
out
std_logic
;
-- emulation of the LEMO input
led_tx_err_n_o
:
out
std_logic
;
ext_sync_i
:
in
std_logic
;
-- sync pulse
led_tx_act_n_o
:
out
std_logic
;
led_rx_err_n_o
:
out
std_logic
;
-- WorldFIP FielDrive
led_rx_act_n_o
:
out
std_logic
fd_rxcdn_i
:
in
std_logic
;
fd_rxd_i
:
in
std_logic
;
);
fd_txer_i
:
in
std_logic
;
fd_wdgn_i
:
in
std_logic
;
fd_rstn_o
:
out
std_logic
;
fd_txck_o
:
out
std_logic
;
fd_txd_o
:
out
std_logic
;
fd_txena_o
:
out
std_logic
;
-- WorldFIP diagnostics ADC power supplies
adc_1v8_shdn_n_o
:
out
std_logic
;
adc_m5v_shdn_n_o
:
out
std_logic
;
adc_5v_en_n_o
:
out
std_logic
;
-- WorldFIP LEDs
led_tx_err_n_o
:
out
std_logic
;
led_tx_act_n_o
:
out
std_logic
;
led_rx_err_n_o
:
out
std_logic
;
led_rx_act_n_o
:
out
std_logic
;
led_out_of_sync_n_o
:
out
std_logic
;
led_sync_n_o
:
out
std_logic
);
end
spec_top
;
end
spec_top
;
architecture
rtl
of
spec_top
is
architecture
rtl
of
spec_top
is
-- TODO: check comments on the WRNC..
-- Host Message Queue configuration
-- Host Message Queue configuration
-- Each CPU has three queues assigned:
-- Each CPU has three queues assigned:
-- 1) a small incoming queue (8 entries x 32 words) for sending host to CPU commands
-- 1) a small incoming queue (8 entries x 32 words) for sending host to CPU commands
...
@@ -168,10 +159,10 @@ constant c_hmq_config : t_wrn_mqueue_config :=
...
@@ -168,10 +159,10 @@ constant c_hmq_config : t_wrn_mqueue_config :=
(
(
out_slot_count
=>
4
,
out_slot_count
=>
4
,
out_slot_config
=>
(
out_slot_config
=>
(
0
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 0 (to host)
0
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 0 (to host)
-- was entries => 4
1
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 1 (to host)
1
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 1 (to host)
-- was entries => 4
2
=>
(
width
=>
128
,
entries
=>
4
),
-- log CPU 0
2
=>
(
width
=>
128
,
entries
=>
4
),
-- log CPU 0
-- was entries => 4
3
=>
(
width
=>
128
,
entries
=>
4
),
-- log CPU 1
3
=>
(
width
=>
128
,
entries
=>
4
),
-- log CPU 1
-- was entries => 4
others
=>
(
0
,
0
)),
others
=>
(
0
,
0
)),
in_slot_count
=>
2
,
in_slot_count
=>
2
,
...
@@ -241,7 +232,7 @@ begin
...
@@ -241,7 +232,7 @@ begin
g_with_wr_phy
=>
false
,
g_with_wr_phy
=>
false
,
g_with_white_rabbit
=>
false
,
g_with_white_rabbit
=>
false
,
g_double_wrnode_core_clock
=>
false
,
g_double_wrnode_core_clock
=>
false
,
g_system_clock_freq
=>
40000000
,
-- 40MHz clock
g_system_clock_freq
=>
100000000
,
-------***-------
g_wr_node_config
=>
c_node_config
)
g_wr_node_config
=>
c_node_config
)
port
map
(
port
map
(
rst_n_sys_o
=>
rst_n_sys
,
rst_n_sys_o
=>
rst_n_sys
,
...
@@ -320,7 +311,7 @@ begin
...
@@ -320,7 +311,7 @@ begin
adc_1v8_shdn_n_o
=>
adc_1v8_shdn_n_o
,
adc_1v8_shdn_n_o
=>
adc_1v8_shdn_n_o
,
adc_m5v_shdn_n_o
=>
adc_m5v_shdn_n_o
,
adc_m5v_shdn_n_o
=>
adc_m5v_shdn_n_o
,
adc_5v_en_n_o
=>
adc_5v_en_n_o
,
adc_5v_en_n_o
=>
adc_5v_en_n_o
,
-- WISHBONE interface with
the GN4124 core
-- WISHBONE interface with
wb_adr_i
=>
fmc_dp_wb_out
.
adr
,
wb_adr_i
=>
fmc_dp_wb_out
.
adr
,
wb_dat_i
=>
fmc_dp_wb_out
.
dat
,
wb_dat_i
=>
fmc_dp_wb_out
.
dat
,
wb_stb_i
=>
fmc_dp_wb_out
.
stb
,
wb_stb_i
=>
fmc_dp_wb_out
.
stb
,
...
@@ -383,10 +374,12 @@ begin
...
@@ -383,10 +374,12 @@ begin
-- -- -- -- -- --
-- -- -- -- -- --
-- led_tx_err_n_o <= led_clk_40m_aux(0);
-- led_tx_err_n_o <= led_clk_40m_aux(0);
led_tx_err_n_o
<=
aux
(
5
);
led_tx_act_n_o
<=
aux
(
3
);
led_tx_act_n_o
<=
aux
(
0
);
led_tx_err_n_o
<=
aux
(
5
);
led_rx_err_n_o
<=
aux
(
2
);
led_rx_err_n_o
<=
aux
(
2
);
led_rx_act_n_o
<=
aux
(
6
);
led_rx_act_n_o
<=
aux
(
6
);
led_out_of_sync_n_o
<=
aux
(
7
);
led_sync_n_o
<=
aux
(
0
);
...
...
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