Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
M
MasterFIP - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
MasterFIP - Gateware
Commits
cf087b1f
Commit
cf087b1f
authored
Feb 23, 2017
by
Evangelia Gousiou
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
corrected fd_rstn_o that was treated as active high
parent
0cea86ef
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
7 changed files
with
234 additions
and
171 deletions
+234
-171
fmc_masterFIP_core.vhd
rtl/fmc_masterFIP_core.vhd
+39
-37
masterfip_rx.vhd
rtl/masterfip_rx.vhd
+6
-6
masterfip_tx.vhd
rtl/masterfip_tx.vhd
+10
-11
wf_package.vhd
rtl/wf_package.vhd
+2
-2
tb_masterFIP.vhd
sim/spec/testbench/tb_masterFIP.vhd
+40
-20
spec_masterfip_mt.vhd
top/spec/spec_masterfip_mt.vhd
+104
-57
synthesis_descriptor.vhd
top/spec/synthesis_descriptor.vhd
+33
-38
No files found.
rtl/fmc_masterFIP_core.vhd
View file @
cf087b1f
This diff is collapsed.
Click to expand it.
rtl/masterfip_rx.vhd
View file @
cf087b1f
...
...
@@ -16,12 +16,12 @@
-- Figure 1 shows the main units/processes; the units RX DESERIALIZER, RX OSC and |
-- RX DEGLITCHER come unmodified from the nanoFIP project. |
-- Figure 2 shows the WorldFIP frame structure; note that the fmc_masterfip_core |
-- i
s completely ignorant of the notion of PDU_TYPE, LGTH, MPS, etc fields inside
|
--
the PAYLOAD part of the frame and is not checking them during reception.
|
-- i
gnores completely the notion of PDU_TYPE, LGTH, MPS, etc fields inside the
|
--
PAYLOAD part of the frame and is not checking them at reception.
|
-- It is the processor (MT) that is handling individually the bytes inside the |
-- PAYLOAD frame field. On the other hand the FSS, CRC and FES fields are
|
--
checked by the masterfip_rx.
|
-- As long as the rx_rst_i is not activated the deserializer
is probing the bus
|
-- PAYLOAD frame field. On the other hand the FSS, CRC and FES fields are
checked
|
--
and validated by the masterfip_rx.
|
-- As long as the rx_rst_i is not activated the deserializer
probes the bus
|
-- looking for a FSS; upon the detection of a FES it activates the rx_crc_wrong_p_o |
-- or rx_fss_crc_fes_ok_p_o accordingly. |
-- |
...
...
@@ -348,8 +348,8 @@ begin
rx_word_index_o
<=
std_logic_vector
(
to_unsigned
(
word32_num
,
7
));
end
architecture
struc
;
end
architecture
struc
;
--=================================================================================================
-- architecture end
--=================================================================================================
...
...
rtl/masterfip_tx.vhd
View file @
cf087b1f
...
...
@@ -15,28 +15,28 @@
-- Description The unit groups the main actions that regard FIELDRIVE data transmission. |
-- Figure 1 shows the main units/processes; the units TX SERIALIZER and TX OSC come |
-- unmodified from the nanoFIP project. |
-- Figure 2 shows the frame structure; note that the fmc_masterfip_core i
s completely
|
--
ignorant of the notion of PDU_TYPE, LGTH, MPS, etc fields inside the PAYLOAD
|
-- Figure 2 shows the frame structure; note that the fmc_masterfip_core i
gnores
|
--
completely the notion of PDU_TYPE, LGTH, MPS, etc fields inside the PAYLOAD
|
-- part of the frame. It is the processor (MT) that is providing all the bytes inside|
-- the PAYLOAD frame field. On the other hand the FSS, CRC and FES fields are |
-- generated by the masterfip_tx. |
-- The serialization starts upon a rising edge on the tx_start_p_i and upon the end |
-- of the FES transmission the masterfip_tx
is activating the tx_end_p_o signal.
|
-- of the FES transmission the masterfip_tx
activates the tx_end_p_o signal.
|
-- |
-- o TX SERIALIZER this unit comes unmodified from the nanoFIP project. |
-- It receives bytes from the processor
(Mock Turtle for example)
|
-- t
rough the tx_frame structure, encodes them in Manchester 2,
|
--
adds the FSS, CRC, FES fields and puts one by one bits to the
|
--
FIELDRIVE output FD_TXD following the synchronization signals
|
--
from the wf_tx_osc unit. It also generates the output FD_TXENA.
|
-- It receives bytes from the processor
trough the
|
-- t
x_frame structure, encodes them in Manchester 2, adds the FSS,
|
--
CRC, FES fields and puts one by one bits to the FIELDRIVE
|
--
output FD_TXD following the synchronization signals from the
|
--
wf_tx_osc unit. It also generates the output FD_TXENA.
|
-- |
-- o TX OSC this unit comes unmodified from the nanoFIP project. |
-- It generates the output FD_TXCK as well as an array of pulses, |
-- tx_sched_p_buff, used for the synchronization of the |
-- TX SERIALIZER's actions. |
-- |
-- o DATA RETRIEVAL this unit copies the bytes provided by the processor
(MT)
|
--
upon the activation of the signal tx_start.
|
-- o DATA RETRIEVAL this unit copies the bytes provided by the processor
upon
|
--
the activation of the signal tx_start.
|
-- |
-- Mock Turtle |
-- ___________________________________________________________ |
...
...
@@ -314,7 +314,6 @@ begin
byte_request_accept_p
<=
byte_request_accept_p_d2
;
-- response to wf_tx_serializer's request
-- for a byte
end
architecture
struc
;
--=================================================================================================
-- architecture end
...
...
rtl/wf_package.vhd
View file @
cf087b1f
...
...
@@ -16,8 +16,8 @@
-- serialization and deserialization; the package is essential for all the modules |
-- coming from the nanoFIP design. |
-- As in the masterFIP design the clk is 100 MHz and in the nanoFIP 40 MHz it was |
-- ne
eded to have a new wf_package. In principle the nanoFIP design could have been
|
--
modified to accept generics rather than constants, however as it is a stable
|
-- ne
cessary to have a new wf_package. In principle the nanoFIP design could have
|
--
been modified to accept generics rather than constants, however as it is a stable
|
-- design it was decided to keep it as it is and use for synthesis this package |
-- rather than the one coming with the nanoFIP submodule. |
-- A different package, the masterfip_pkg is used in the masterfip design for all |
...
...
sim/spec/testbench/tb_masterFIP.vhd
View file @
cf087b1f
----------------------------------------------------------------------------------------------------
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : TDC test-bench (tb_masterFIP)
-- author : G. Penacoba
-- date : May 2011
-- version : Revision 1
-- description : top module for test-bench
-- dependencies:
-- references :
-- modified by :
--
----------------------------------------------------------------------------------------------------
-- last changes:
----------------------------------------------------------------------------------------------------
-- to do:
----------------------------------------------------------------------------------------------------
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- tb_masterFIP |
-- |
---------------------------------------------------------------------------------------------------
-- File tb_masterFIP.vhd |
-- |
-- Description Simple test bench of the masterFIP design. The test bench is triggering the |
-- fmc_masterfip_core through the PCIe host interface, that is not passing through |
-- Mock Turtle. The WorldFIP exchange, as specified in the masterFIP_test.vec |
-- consists of: |
-- fmc_masterfip_core: sends ID_DAT |
-- fmc_masterfip_core: sends RD_DAT |
-- fmc_masterfip_core: sends ID_DAT |
-- fmc_masterfip_core: expects RD_DAT from the nanoFIP node |
-- etc.. |
-- |
-- Platform FPGA-generic |
-- |
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, please download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
IEEE
.
numeric_std
.
all
;
library
nano
FIP
_lib
;
use
nano
FIP
_lib
.
all
;
library
nano
fip
_lib
;
use
nano
fip
_lib
.
all
;
library
work
;
use
work
.
wishbone_pkg
.
all
;
...
...
top/spec/spec_masterfip_mt.vhd
View file @
cf087b1f
This diff is collapsed.
Click to expand it.
top/spec/synthesis_descriptor.vhd
View file @
cf087b1f
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- synthesis_descriptor |
-- |
---------------------------------------------------------------------------------------------------
-- File synthesis_descriptor.vhd |
-- |
-- Description SDB descriptor for the top level of the masterFIP on a SPEC carrier. |
-- Contains synthesis & source repository information. |
-- |
-- Platform FPGA-generic |
-- |
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, please download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
...
...
@@ -46,12 +41,12 @@ constant c_sdb_synthesis_info : t_sdb_synthesis :=
syn_commit_id
=>
"00000000000000000000000000000000"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000147"
,
syn_date
=>
x"201
60128
"
,
syn_date
=>
x"201
72202
"
,
syn_username
=>
"egousiou "
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
repo_url
=>
"
http://svn.ohwr.org/projects/masterFIP
"
repo_url
=>
"
git@ohwr.org:cern-fip/masterfip/masterfip-gw.git
"
);
end
package
synthesis_descriptor
;
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment