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MasterFIP - Gateware
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MasterFIP - Gateware
Commits
a3af67a7
Commit
a3af67a7
authored
Feb 09, 2018
by
Tomasz Wlostowski
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Added HDLMake manifests & synthesis descriptor file
parent
05b8b96d
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3 changed files
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87 additions
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0 deletions
+87
-0
Manifest.py
rtl/Manifest.py
+21
-0
Manifest.py
top/spec/Manifest.py
+14
-0
synthesis_descriptor.vhd
top/spec/synthesis_descriptor.vhd
+52
-0
No files found.
rtl/Manifest.py
0 → 100644
View file @
a3af67a7
files
=
[
"decr_counter.vhd"
,
"fmc_masterFIP_core.vhd"
,
"incr_counter.vhd"
,
"masterFIP_pkg.vhd"
,
"masterfip_rx.vhd"
,
"masterfip_tx.vhd"
,
"masterfip_wbgen2_csr.vhd"
,
"masterfip_wbgen2_pkg.vhd"
,
"wf_package.vhd"
,
"../ip_cores/nanofip/src/wf_crc.vhd"
,
"../ip_cores/nanofip/src/wf_decr_counter.vhd"
,
"../ip_cores/nanofip/src/wf_fd_receiver.vhd"
,
"../ip_cores/nanofip/src/wf_fd_transmitter.vhd"
,
"../ip_cores/nanofip/src/wf_incr_counter.vhd"
,
"../ip_cores/nanofip/src/wf_rx_deglitcher.vhd"
,
"../ip_cores/nanofip/src/wf_rx_deserializer.vhd"
,
"../ip_cores/nanofip/src/wf_rx_osc.vhd"
,
"../ip_cores/nanofip/src/wf_tx_osc.vhd"
,
"../ip_cores/nanofip/src/wf_tx_serializer.vhd"
]
top/spec/Manifest.py
0 → 100644
View file @
a3af67a7
files
=
[
"synthesis_descriptor.vhd"
,
"spec_masterfip_mt.vhd"
,
"spec_masterfip_mt.ucf"
]
fetchto
=
"../../ip_cores"
modules
=
{
"local"
:
[
"../../rtl"
,
"../../ip_cores/wr-node-core/hdl/rtl/wrnc"
,
"../../ip_cores/wr-node-core/hdl/top/spec/node_template"
,
"../../ip_cores/gn4124-core"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/etherbone-core"
,
"../../ip_cores/wr-cores"
]
};
\ No newline at end of file
top/spec/synthesis_descriptor.vhd
0 → 100644
View file @
a3af67a7
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- synthesis_descriptor |
-- |
---------------------------------------------------------------------------------------------------
-- File synthesis_descriptor.vhd |
-- |
-- Description SDB descriptor for the top level of the masterFIP on a SPEC carrier. |
-- Contains synthesis & source repository information. |
-- |
-- Platform FPGA-generic |
-- |
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, please download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
synthesis_descriptor
is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"masterFIP_MT "
,
syn_commit_id
=>
"00000000000000000000000000000000"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000147"
,
syn_date
=>
x"20172202"
,
syn_username
=>
"egousiou "
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
repo_url
=>
"git@ohwr.org:cern-fip/masterfip/masterfip-gw.git "
);
end
package
synthesis_descriptor
;
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