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MasterFIP - Gateware
Commit 9aa29601 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- changes on the test bench; added nanoFIP node as a library 

- added 2 out HMQs
- changed cpu_mem_sizes
- added crossbar that gives access to both CPUs to the fmc_masterfip_core
- added logic for the fd_wdgn and fd_txerr handling
- relevant changes on fmc_masterfip_csr.wb regs
parent 6ddb678f
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rtl/fmc_masterFIP_core.vhd
View file @ 9aa29601
......@@ -218,7 +218,7 @@ architecture rtl of fmc_masterFIP_core is
signal tx_rst, tx_host_rst, tx_host_rst_p, fd_txd, fd_txck : std_logic;
signal tx_frame : tx_frame_t;
signal tx_ctrl_byte : std_logic_vector(7 downto 0);
signal tx_bytes_num, tx_byte_index : std_logic_vector(8 downto 0); -- up to 263 bytes
signal tx_bytes_num, tx_byte_index : std_logic_vector(15 downto 0); -- up to 263 bytes
-- rx
signal rx_host_rst, rx_host_rst_p, rx_rst : std_logic;
signal rx_fss_received_p, rx_fss_received : std_logic;
......@@ -227,6 +227,10 @@ architecture rtl of fmc_masterFIP_core is
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_bytes_num : std_logic_vector(15 downto 0);
-- fd_wdgn, fd_txer
signal fd_wdgn_tstamp, fd_txer_tstamp : std_logic_vector(30 downto 0);
signal fd_wdg, fd_wdgn_p,fd_txer,fd_txer_p, fd_txer_cnt_reinit : std_logic;
signal fd_txer_cnt : std_logic_vector(31 downto 0);
-- ADC
signal adc_sec_conn_n, adc_prim_conn_n : std_logic;
-- ext_sync
......@@ -320,12 +324,16 @@ begin
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame; then converted to 1-tick-long pulse
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start
-- tx status
mf_tx_stat_stop_i => tx_completed, -- 16x25ns long pulse upon the end of delivery of a frame
mf_tx_stat_byte_index_i => tx_byte_index, -- index of current byte being serialized
mf_tx_stat_stop_i => tx_completed, -- 16x10ns long pulse upon the end of delivery of a frame
mf_tx_stat_curr_byte_indx_i => tx_byte_index, -- index of current byte being serialized
mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer
mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog, signal comes from the FIELDRIVE
mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr, signal comes from the FIELDRIVE
-- rx control/status
-- fd_wdgn
mf_fd_wdgn_tstamp_i => fd_wdgn_tstamp,
mf_fd_wdgn_act_i => fd_wdg,
-- fd_txer
mf_fd_txer_cnt_i => fd_txer_cnt,
mf_fd_txer_tstamp_i => fd_txer_tstamp,
-- rx control
mf_rx_ctrl_rst_o => rx_host_rst, -- note: this is not a pulse
-- rx status
mf_rx_stat_pream_ok_i => rx_fss_received,
......@@ -539,6 +547,11 @@ begin
---------------------------------------------------------------------------------------------------
-- macrocycle counter --
---------------------------------------------------------------------------------------------------
-- in an application where an external synchronization pulse is expected for every macrocyle,
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time
-- counter counting the macrocycle time
cmp_macrocycle_time_cnt: decr_counter
generic map(width => 31)
......@@ -561,29 +574,6 @@ begin
data_i => macrocyc_host_load,
ppulse_o => macrocyc_host_load_p);
-- in an application where an external synchronization pulse is expected for every macrocyle,
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time
cmp_out_of_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => macrocyc_cnt_zero_p,
extended_o => out_of_sync_led);
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => ext_sync_p,
extended_o => sync_led);
-- counter counting the number of macrocycles; when it fills up it restarts
cmp_macrocycles_cnt:incr_counter
generic map(g_counter_lgth => 32)
......@@ -709,7 +699,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extending the rx_crc_wrong_p until a core_rst or rx_rst is received
-- extending the until a core_rst or rx_rst is received
p_rx_crc_wrong_extend : process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -801,17 +791,113 @@ begin
data_i => tx_host_rst,
ppulse_o => tx_host_rst_p);
-- extension of the tx_completed_p so as to ensure capturing by the wrnc
-- TODO: keep high and only reset upon reading from the MT
cmp_tx_extend_p : gc_extend_pulse
generic map (g_width => 32) -- 32 ticks long
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extending the tx_completed_p until a core_rst or rx_rst is received
p_tx_completed_extend : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or tx_host_rst_p = '1' or tx_start_p = '1') then
tx_completed <= '0';
else
if tx_completed_p = '1' then
tx_completed <= '1';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- FielDrive TXERR, WDGN --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- edge detection on the fd_wdgn_i signal
cmp_fd_wdgn_i_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "negative")
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_wdgn_i,
ppulse_o => fd_wdgn_p);
-- process that registers the macrocycle_cnt value upon the last fd_wdgn_p of a macrocycle
p_fd_wdgn_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0') then
fd_wdg <= '0';
fd_wdgn_tstamp <= macrocyc_cnt;
else
if fd_wdgn_p = '1' then
fd_wdg <= '1';
fd_wdgn_tstamp <= macrocyc_cnt;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- edge detection on the fd_txer_i signal
cmp_fd_txer_i_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "negative")
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_txer_i,
ppulse_o => fd_txer_p);
-- counter counting the number of fd_wdgn_p
cmp_fd_wdgn_cnt:incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
counter_incr_i => fd_txer_p,
counter_reinit_i => fd_txer_cnt_reinit,
counter_is_full_o => open,
counter_o => fd_txer_cnt);
fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0'
else '0';
-- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle
p_fd_txer_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0') then
fd_txer <= '1';
fd_txer_tstamp <= macrocyc_cnt;
else
if fd_txer_p = '1' then
fd_txer <= '0';
fd_txer_tstamp <= macrocyc_cnt;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- LEDs --
---------------------------------------------------------------------------------------------------
cmp_out_of_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => tx_completed_p,
extended_o => tx_completed);
pulse_i => macrocyc_cnt_zero_p,
extended_o => out_of_sync_led);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => ext_sync_p,
extended_o => sync_led);
---------------------------------------------------------------------------------------------------
-- aux --
---------------------------------------------------------------------------------------------------
......
rtl/fmc_masterfip_csr.vhd
View file @ 9aa29601
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 03/02/16 17:13:05
-- Created : 03/08/16 16:14:18
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -85,17 +85,21 @@ entity fmc_masterfip_csr is
-- Port for BIT field: 'tx strt' in reg: 'tx ctrl'
mf_tx_ctrl_start_o : out std_logic;
-- Port for std_logic_vector field: 'tx number of bytes' in reg: 'tx ctrl'
mf_tx_ctrl_bytes_num_o : out std_logic_vector(8 downto 0);
mf_tx_ctrl_bytes_num_o : out std_logic_vector(15 downto 0);
-- Port for BIT field: 'tx ended' in reg: 'tx status'
mf_tx_stat_stop_i : in std_logic;
-- Port for std_logic_vector field: 'tx current byte' in reg: 'tx status'
mf_tx_stat_byte_index_i : in std_logic_vector(8 downto 0);
-- Port for BIT field: 'tx enable' in reg: 'tx status'
mf_tx_stat_ena_i : in std_logic;
-- Port for BIT field: 'fd watchdog' in reg: 'fieldrive status'
mf_fd_wdgn_i : in std_logic;
-- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
mf_fd_txer_i : in std_logic;
-- Port for std_logic_vector field: 'tx status current byte index' in reg: 'tx status'
mf_tx_stat_curr_byte_indx_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'fd_wdgn_tstamp' in reg: 'fieldrive wdgn'
mf_fd_wdgn_tstamp_i : in std_logic_vector(30 downto 0);
-- Port for BIT field: 'fd_wdg_act' in reg: 'fieldrive wdgn'
mf_fd_wdgn_act_i : in std_logic;
-- Port for std_logic_vector field: 'fd_txer_cnt' in reg: 'fieldrive txer cnt'
mf_fd_txer_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fd_txer_tstamp' in reg: 'fieldrive txer tstamp'
mf_fd_txer_tstamp_i : in std_logic_vector(30 downto 0);
-- Port for BIT field: 'rx rst' in reg: 'rx ctrl'
mf_rx_ctrl_rst_o : out std_logic;
-- Port for BIT field: 'rx preamble detected' in reg: 'rx status'
......@@ -406,7 +410,7 @@ signal mf_silen_lgth_int : std_logic_vector(30 downto 0);
signal mf_silen_start_int : std_logic ;
signal mf_tx_ctrl_rst_int : std_logic ;
signal mf_tx_ctrl_start_int : std_logic ;
signal mf_tx_ctrl_bytes_num_int : std_logic_vector(8 downto 0);
signal mf_tx_ctrl_bytes_num_int : std_logic_vector(15 downto 0);
signal mf_rx_ctrl_rst_int : std_logic ;
signal mf_tx_data_ctrl_int : std_logic_vector(7 downto 0);
signal mf_tx_data_reg1_int : std_logic_vector(31 downto 0);
......@@ -525,7 +529,7 @@ begin
mf_silen_start_int <= '0';
mf_tx_ctrl_rst_int <= '0';
mf_tx_ctrl_start_int <= '0';
mf_tx_ctrl_bytes_num_int <= "000000000";
mf_tx_ctrl_bytes_num_int <= "0000000000000000";
mf_rx_ctrl_rst_int <= '0';
mf_tx_data_ctrl_int <= "00000000";
mf_tx_data_reg1_int <= "00000000000000000000000000000000";
......@@ -846,24 +850,17 @@ begin
if (wb_we_i = '1') then
mf_tx_ctrl_rst_int <= wrdata_reg(0);
mf_tx_ctrl_start_int <= wrdata_reg(1);
mf_tx_ctrl_bytes_num_int <= wrdata_reg(16 downto 8);
mf_tx_ctrl_bytes_num_int <= wrdata_reg(23 downto 8);
end if;
rddata_reg(0) <= mf_tx_ctrl_rst_int;
rddata_reg(1) <= mf_tx_ctrl_start_int;
rddata_reg(16 downto 8) <= mf_tx_ctrl_bytes_num_int;
rddata_reg(23 downto 8) <= mf_tx_ctrl_bytes_num_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -878,8 +875,8 @@ begin
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_tx_stat_stop_i;
rddata_reg(16 downto 8) <= mf_tx_stat_byte_index_i;
rddata_reg(24) <= mf_tx_stat_ena_i;
rddata_reg(8) <= mf_tx_stat_ena_i;
rddata_reg(24 downto 9) <= mf_tx_stat_curr_byte_indx_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -887,13 +884,6 @@ begin
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -906,41 +896,24 @@ begin
when "00010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_fd_wdgn_i;
rddata_reg(1) <= mf_fd_txer_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(30 downto 0) <= mf_fd_wdgn_tstamp_i;
rddata_reg(31) <= mf_fd_wdgn_act_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_fd_txer_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_fd_txer_tstamp_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010011" =>
if (wb_we_i = '1') then
mf_rx_ctrl_rst_int <= wrdata_reg(0);
end if;
......@@ -978,7 +951,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010010" =>
when "00010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_rx_stat_pream_ok_i;
......@@ -1000,7 +973,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010011" =>
when "00010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= mf_rx_stat_curr_byte_indx_i;
......@@ -1022,7 +995,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010100" =>
when "00010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= mf_rx_data_ctrl_i;
......@@ -1052,409 +1025,409 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010101" =>
when "00010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010110" =>
when "00011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010111" =>
when "00011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011000" =>
when "00011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011001" =>
when "00011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011010" =>
when "00011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011011" =>
when "00011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011100" =>
when "00011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg8_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011101" =>
when "00011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg9_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011110" =>
when "00100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg10_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011111" =>
when "00100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg11_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100000" =>
when "00100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg12_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100001" =>
when "00100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg13_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100010" =>
when "00100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg14_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100011" =>
when "00100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg15_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100100" =>
when "00100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg16_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100101" =>
when "00100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg17_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100110" =>
when "00101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg18_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100111" =>
when "00101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg19_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101000" =>
when "00101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg20_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101001" =>
when "00101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg21_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101010" =>
when "00101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg22_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101011" =>
when "00101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg23_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101100" =>
when "00101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg24_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101101" =>
when "00101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg25_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101110" =>
when "00110000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg26_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101111" =>
when "00110001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg27_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110000" =>
when "00110010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg28_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110001" =>
when "00110011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg29_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110010" =>
when "00110100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg30_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110011" =>
when "00110101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg31_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110100" =>
when "00110110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg32_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110101" =>
when "00110111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg33_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110110" =>
when "00111000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg34_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110111" =>
when "00111001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg35_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111000" =>
when "00111010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg36_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111001" =>
when "00111011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg37_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111010" =>
when "00111100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg38_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111011" =>
when "00111101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg39_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111100" =>
when "00111110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg40_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111101" =>
when "00111111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg41_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111110" =>
when "01000000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg42_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111111" =>
when "01000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg43_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000000" =>
when "01000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg44_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000001" =>
when "01000011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg45_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000010" =>
when "01000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg46_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000011" =>
when "01000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg47_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000100" =>
when "01000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg48_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000101" =>
when "01000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg49_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000110" =>
when "01001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg50_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000111" =>
when "01001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg51_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001000" =>
when "01001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg52_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001001" =>
when "01001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg53_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001010" =>
when "01001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg54_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001011" =>
when "01001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg55_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001100" =>
when "01001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg56_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001101" =>
when "01001111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg57_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001110" =>
when "01010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg58_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001111" =>
when "01010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg59_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010000" =>
when "01010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg60_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010001" =>
when "01010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg61_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010010" =>
when "01010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg62_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010011" =>
when "01010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg63_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010100" =>
when "01010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg64_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010101" =>
when "01010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg65_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010110" =>
when "01011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg66_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010111" =>
when "01011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg67_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011000" =>
when "01011010" =>
if (wb_we_i = '1') then
mf_tx_data_ctrl_int <= wrdata_reg(7 downto 0);
end if;
......@@ -1485,469 +1458,469 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011001" =>
when "01011011" =>
if (wb_we_i = '1') then
mf_tx_data_reg1_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011010" =>
when "01011100" =>
if (wb_we_i = '1') then
mf_tx_data_reg2_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011011" =>
when "01011101" =>
if (wb_we_i = '1') then
mf_tx_data_reg3_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011100" =>
when "01011110" =>
if (wb_we_i = '1') then
mf_tx_data_reg4_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg4_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011101" =>
when "01011111" =>
if (wb_we_i = '1') then
mf_tx_data_reg5_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg5_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011110" =>
when "01100000" =>
if (wb_we_i = '1') then
mf_tx_data_reg6_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg6_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011111" =>
when "01100001" =>
if (wb_we_i = '1') then
mf_tx_data_reg7_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg7_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100000" =>
when "01100010" =>
if (wb_we_i = '1') then
mf_tx_data_reg8_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg8_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100001" =>
when "01100011" =>
if (wb_we_i = '1') then
mf_tx_data_reg9_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg9_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100010" =>
when "01100100" =>
if (wb_we_i = '1') then
mf_tx_data_reg10_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg10_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100011" =>
when "01100101" =>
if (wb_we_i = '1') then
mf_tx_data_reg11_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg11_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100100" =>
when "01100110" =>
if (wb_we_i = '1') then
mf_tx_data_reg12_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg12_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100101" =>
when "01100111" =>
if (wb_we_i = '1') then
mf_tx_data_reg13_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg13_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100110" =>
when "01101000" =>
if (wb_we_i = '1') then
mf_tx_data_reg14_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg14_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100111" =>
when "01101001" =>
if (wb_we_i = '1') then
mf_tx_data_reg15_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg15_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101000" =>
when "01101010" =>
if (wb_we_i = '1') then
mf_tx_data_reg16_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg16_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101001" =>
when "01101011" =>
if (wb_we_i = '1') then
mf_tx_data_reg17_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg17_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101010" =>
when "01101100" =>
if (wb_we_i = '1') then
mf_tx_data_reg18_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg18_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101011" =>
when "01101101" =>
if (wb_we_i = '1') then
mf_tx_data_reg19_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg19_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101100" =>
when "01101110" =>
if (wb_we_i = '1') then
mf_tx_data_reg20_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg20_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101101" =>
when "01101111" =>
if (wb_we_i = '1') then
mf_tx_data_reg21_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg21_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101110" =>
when "01110000" =>
if (wb_we_i = '1') then
mf_tx_data_reg22_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg22_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101111" =>
when "01110001" =>
if (wb_we_i = '1') then
mf_tx_data_reg23_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg23_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110000" =>
when "01110010" =>
if (wb_we_i = '1') then
mf_tx_data_reg24_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg24_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110001" =>
when "01110011" =>
if (wb_we_i = '1') then
mf_tx_data_reg25_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg25_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110010" =>
when "01110100" =>
if (wb_we_i = '1') then
mf_tx_data_reg26_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg26_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110011" =>
when "01110101" =>
if (wb_we_i = '1') then
mf_tx_data_reg27_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg27_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110100" =>
when "01110110" =>
if (wb_we_i = '1') then
mf_tx_data_reg28_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg28_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110101" =>
when "01110111" =>
if (wb_we_i = '1') then
mf_tx_data_reg29_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg29_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110110" =>
when "01111000" =>
if (wb_we_i = '1') then
mf_tx_data_reg30_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg30_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110111" =>
when "01111001" =>
if (wb_we_i = '1') then
mf_tx_data_reg31_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg31_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111000" =>
when "01111010" =>
if (wb_we_i = '1') then
mf_tx_data_reg32_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg32_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111001" =>
when "01111011" =>
if (wb_we_i = '1') then
mf_tx_data_reg33_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg33_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111010" =>
when "01111100" =>
if (wb_we_i = '1') then
mf_tx_data_reg34_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg34_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111011" =>
when "01111101" =>
if (wb_we_i = '1') then
mf_tx_data_reg35_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg35_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111100" =>
when "01111110" =>
if (wb_we_i = '1') then
mf_tx_data_reg36_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg36_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111101" =>
when "01111111" =>
if (wb_we_i = '1') then
mf_tx_data_reg37_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg37_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111110" =>
when "10000000" =>
if (wb_we_i = '1') then
mf_tx_data_reg38_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg38_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111111" =>
when "10000001" =>
if (wb_we_i = '1') then
mf_tx_data_reg39_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg39_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000000" =>
when "10000010" =>
if (wb_we_i = '1') then
mf_tx_data_reg40_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg40_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000001" =>
when "10000011" =>
if (wb_we_i = '1') then
mf_tx_data_reg41_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg41_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000010" =>
when "10000100" =>
if (wb_we_i = '1') then
mf_tx_data_reg42_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg42_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000011" =>
when "10000101" =>
if (wb_we_i = '1') then
mf_tx_data_reg43_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg43_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000100" =>
when "10000110" =>
if (wb_we_i = '1') then
mf_tx_data_reg44_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg44_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000101" =>
when "10000111" =>
if (wb_we_i = '1') then
mf_tx_data_reg45_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg45_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000110" =>
when "10001000" =>
if (wb_we_i = '1') then
mf_tx_data_reg46_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg46_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000111" =>
when "10001001" =>
if (wb_we_i = '1') then
mf_tx_data_reg47_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg47_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001000" =>
when "10001010" =>
if (wb_we_i = '1') then
mf_tx_data_reg48_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg48_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001001" =>
when "10001011" =>
if (wb_we_i = '1') then
mf_tx_data_reg49_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg49_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001010" =>
when "10001100" =>
if (wb_we_i = '1') then
mf_tx_data_reg50_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg50_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001011" =>
when "10001101" =>
if (wb_we_i = '1') then
mf_tx_data_reg51_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg51_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001100" =>
when "10001110" =>
if (wb_we_i = '1') then
mf_tx_data_reg52_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg52_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001101" =>
when "10001111" =>
if (wb_we_i = '1') then
mf_tx_data_reg53_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg53_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001110" =>
when "10010000" =>
if (wb_we_i = '1') then
mf_tx_data_reg54_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg54_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001111" =>
when "10010001" =>
if (wb_we_i = '1') then
mf_tx_data_reg55_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg55_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010000" =>
when "10010010" =>
if (wb_we_i = '1') then
mf_tx_data_reg56_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg56_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010001" =>
when "10010011" =>
if (wb_we_i = '1') then
mf_tx_data_reg57_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg57_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010010" =>
when "10010100" =>
if (wb_we_i = '1') then
mf_tx_data_reg58_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg58_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010011" =>
when "10010101" =>
if (wb_we_i = '1') then
mf_tx_data_reg59_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg59_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010100" =>
when "10010110" =>
if (wb_we_i = '1') then
mf_tx_data_reg60_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg60_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010101" =>
when "10010111" =>
if (wb_we_i = '1') then
mf_tx_data_reg61_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg61_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010110" =>
when "10011000" =>
if (wb_we_i = '1') then
mf_tx_data_reg62_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg62_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010111" =>
when "10011001" =>
if (wb_we_i = '1') then
mf_tx_data_reg63_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg63_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011000" =>
when "10011010" =>
if (wb_we_i = '1') then
mf_tx_data_reg64_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg64_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011001" =>
when "10011011" =>
if (wb_we_i = '1') then
mf_tx_data_reg65_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg65_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011010" =>
when "10011100" =>
if (wb_we_i = '1') then
mf_tx_data_reg66_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg66_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011011" =>
when "10011101" =>
if (wb_we_i = '1') then
mf_tx_data_reg67_int <= wrdata_reg(31 downto 0);
end if;
......@@ -2021,10 +1994,12 @@ begin
-- tx number of bytes
mf_tx_ctrl_bytes_num_o <= mf_tx_ctrl_bytes_num_int;
-- tx ended
-- tx current byte
-- tx enable
-- fd watchdog
-- fd transmitter error
-- tx status current byte index
-- fd_wdgn_tstamp
-- fd_wdg_act
-- fd_txer_cnt
-- fd_txer_tstamp
-- rx rst
mf_rx_ctrl_rst_o <= mf_rx_ctrl_rst_int;
-- rx preamble detected
......
rtl/masterFIP_pkg.vhd
View file @ 9aa29601
......@@ -226,13 +226,16 @@ package masterFIP_pkg is
mf_tx_ctrl_rst_o : out std_logic;
mf_tx_ctrl_start_o : out std_logic;
mf_tx_ctrl_bytes_num_o : out std_logic_vector(8 downto 0);
mf_tx_ctrl_bytes_num_o : out std_logic_vector(15 downto 0);
mf_tx_stat_stop_i : in std_logic;
mf_tx_stat_byte_index_i : in std_logic_vector(8 downto 0);
mf_tx_stat_curr_byte_indx_i : in std_logic_vector(15 downto 0);
mf_tx_stat_ena_i : in std_logic;
mf_fd_wdgn_i : in std_logic;
mf_fd_txer_i : in std_logic;
mf_fd_wdgn_tstamp_i : in std_logic_vector(30 downto 0);
mf_fd_wdgn_act_i : in std_logic;
mf_fd_txer_cnt_i : in std_logic_vector(31 downto 0);
mf_fd_txer_tstamp_i : in std_logic_vector(30 downto 0);
mf_rx_ctrl_rst_o : out std_logic;
mf_rx_stat_pream_ok_i : in std_logic;
......@@ -493,11 +496,11 @@ package masterFIP_pkg is
speed_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector (8 downto 0);
tx_bytes_num_i : in std_logic_vector (15 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
tx_byte_index_o : out std_logic_vector (8 downto 0);
tx_byte_index_o : out std_logic_vector (15 downto 0);
tx_end_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
......
rtl/masterfip_tx.vhd
View file @ 9aa29601
......@@ -107,7 +107,7 @@ entity masterfip_tx is port(
-- this represents the max length of a frame
-- upon tx_start_p_i only tx_bytes_num_i are read and transmitted
tx_bytes_num_i : in std_logic_vector(8 downto 0); -- number of bytes to be serialized
tx_bytes_num_i : in std_logic_vector(15 downto 0); -- number of bytes to be serialized
tx_ctrl_byte_i : in std_logic_vector(7 downto 0); -- frame CTRL byte
......@@ -115,7 +115,7 @@ entity masterfip_tx is port(
-- OUTPUTS
tx_byte_index_o : out std_logic_vector(8 downto 0); -- index of the byte currently being serialized (0-262)
tx_byte_index_o : out std_logic_vector(15 downto 0); -- index of the byte currently being serialized (0-262)
tx_end_p_o : out std_logic; -- pulse upon termination of a transmission (CRC & FES included)
......@@ -134,13 +134,13 @@ end entity masterfip_tx;
architecture struc of masterfip_tx is
-- frame bytes
signal prod_bytes_c : unsigned(8 downto 0);
signal prod_bytes_c : unsigned(15 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0);
signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 66;
signal word32 : std_logic_vector(31 downto 0);
-- bytes counter
signal bytes_num : std_logic_vector(8 downto 0);
signal bytes_num : std_logic_vector(15 downto 0);
signal prod_data_lgth_match : std_logic;
signal last_data_byte_p, last_data_byte_p_d : std_logic;
-- wf_tx_osc
......@@ -205,7 +205,7 @@ begin
-- Instantiation of a wf_incr_counter for the counting of the number of the bytes that are
-- being serialized.
cmp_tx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 9)
generic map(g_counter_lgth => 16)
port map(
uclk_i => clk_i,
counter_reinit_i => tx_start_p_i,
......
rtl/wbgen/fmc_masterfip_csr.h
View file @ 9aa29601
......@@ -3,7 +3,7 @@
* File : fmc_masterfip_csr.h
* Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
* Created : 12/04/15 19:19:41
* Created : 03/08/16 16:14:19
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -71,10 +71,10 @@
/* definitions for field: termination enable in reg: ext sync */
#define MF_EXT_SYNC_TERM_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tranceiver direction in reg: ext sync */
/* definitions for field: transceiver direction in reg: ext sync */
#define MF_EXT_SYNC_DIR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tranceiver output enable in reg: ext sync */
/* definitions for field: transceiver output enable in reg: ext sync */
#define MF_EXT_SYNC_OE WBGEN2_GEN_MASK(2, 1)
/* definitions for field: test pulse in reg: ext sync */
......@@ -85,9 +85,7 @@
/* definitions for register: ext sync pulses cnt */
/* definitions for register: bus termination */
/* definitions for register: speed */
/* definitions for register: bus speed */
/* definitions for register: macrocycle lgth */
......@@ -139,32 +137,39 @@
#define MF_TX_CTRL_START WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tx number of bytes in reg: tx ctrl */
#define MF_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 9)
#define MF_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MF_TX_CTRL_BYTES_NUM_SHIFT 8
#define MF_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 9)
#define MF_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 9)
#define MF_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MF_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: tx status */
/* definitions for field: tx ended in reg: tx status */
#define MF_TX_STAT_STOP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx current byte in reg: tx status */
#define MF_TX_STAT_BYTE_INDEX_MASK WBGEN2_GEN_MASK(8, 9)
#define MF_TX_STAT_BYTE_INDEX_SHIFT 8
#define MF_TX_STAT_BYTE_INDEX_W(value) WBGEN2_GEN_WRITE(value, 8, 9)
#define MF_TX_STAT_BYTE_INDEX_R(reg) WBGEN2_GEN_READ(reg, 8, 9)
/* definitions for field: tx enable in reg: tx status */
#define MF_TX_STAT_ENA WBGEN2_GEN_MASK(24, 1)
#define MF_TX_STAT_ENA WBGEN2_GEN_MASK(8, 1)
/* definitions for field: tx status current byte index in reg: tx status */
#define MF_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(9, 16)
#define MF_TX_STAT_CURR_BYTE_INDX_SHIFT 9
#define MF_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 9, 16)
#define MF_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 9, 16)
/* definitions for register: fieldrive wdgn */
/* definitions for field: fd_wdgn_tstamp in reg: fieldrive wdgn */
#define MF_FD_WDGN_TSTAMP_MASK WBGEN2_GEN_MASK(0, 31)
#define MF_FD_WDGN_TSTAMP_SHIFT 0
#define MF_FD_WDGN_TSTAMP_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MF_FD_WDGN_TSTAMP_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for register: fieldrive status */
/* definitions for field: fd_wdg_act in reg: fieldrive wdgn */
#define MF_FD_WDGN_ACT WBGEN2_GEN_MASK(31, 1)
/* definitions for field: fd watchdog in reg: fieldrive status */
#define MF_FD_WDGN WBGEN2_GEN_MASK(0, 1)
/* definitions for register: fieldrive txer cnt */
/* definitions for field: fd transmitter error in reg: fieldrive status */
#define MF_FD_TXER WBGEN2_GEN_MASK(1, 1)
/* definitions for register: fieldrive txer tstamp */
/* definitions for register: rx ctrl */
......@@ -179,20 +184,16 @@
/* definitions for field: rx frame ok in reg: rx status */
#define MF_RX_STAT_FRAME_OK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: rx frame error in reg: rx status */
#define MF_RX_STAT_FRAME_ERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: rx frame error code in reg: rx status */
#define MF_RX_STAT_FRAME_ERR_CODE_MASK WBGEN2_GEN_MASK(3, 3)
#define MF_RX_STAT_FRAME_ERR_CODE_SHIFT 3
#define MF_RX_STAT_FRAME_ERR_CODE_W(value) WBGEN2_GEN_WRITE(value, 3, 3)
#define MF_RX_STAT_FRAME_ERR_CODE_R(reg) WBGEN2_GEN_READ(reg, 3, 3)
/* definitions for field: rx frame crc error in reg: rx status */
#define MF_RX_STAT_FRAME_CRC_ERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: rx number of data bytes in reg: rx status */
#define MF_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 9)
#define MF_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MF_RX_STAT_BYTES_NUM_SHIFT 8
#define MF_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 9)
#define MF_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 9)
#define MF_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MF_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: rx status current byte index */
/* definitions for register: rx data ctrl byte */
......@@ -328,6 +329,8 @@
/* definitions for register: rx data reg66 */
/* definitions for register: rx data reg67 */
/* definitions for register: tx ctrl byte */
/* definitions for register: tx data reg1 */
......@@ -461,6 +464,8 @@
/* definitions for register: tx data reg65 */
/* definitions for register: tx data reg66 */
/* definitions for register: tx data reg67 */
/* [0x0]: REG rstn */
#define MF_REG_RSTN 0x00000000
/* [0x4]: REG id */
......@@ -473,300 +478,308 @@
#define MF_REG_EXT_SYNC 0x00000010
/* [0x14]: REG ext sync pulses cnt */
#define MF_REG_EXT_SYNC_P_CNT 0x00000014
/* [0x18]: REG bus termination */
#define MF_REG_BUS_TERM_EN_N 0x00000018
/* [0x1c]: REG speed */
#define MF_REG_SPEED 0x0000001c
/* [0x20]: REG macrocycle lgth */
#define MF_REG_MACROCYC 0x00000020
/* [0x24]: REG turnaround lgth */
#define MF_REG_TURNAR 0x00000024
/* [0x28]: REG silence lgth */
#define MF_REG_SILEN 0x00000028
/* [0x2c]: REG macrocycle time cnt */
#define MF_REG_MACROCYC_TIME_CNT 0x0000002c
/* [0x30]: REG macrocycles number cnt */
#define MF_REG_MACROCYC_NUM_CNT 0x00000030
/* [0x34]: REG turnaround time cnt */
#define MF_REG_TURNAR_TIME_CNT 0x00000034
/* [0x38]: REG silence time cnt */
#define MF_REG_SILEN_TIME_CNT 0x00000038
/* [0x3c]: REG tx ctrl */
#define MF_REG_TX_CTRL 0x0000003c
/* [0x40]: REG tx status */
#define MF_REG_TX_STAT 0x00000040
/* [0x44]: REG fieldrive status */
#define MF_REG_FD 0x00000044
/* [0x48]: REG rx ctrl */
#define MF_REG_RX_CTRL 0x00000048
/* [0x4c]: REG rx status */
#define MF_REG_RX_STAT 0x0000004c
/* [0x50]: REG rx data ctrl byte */
#define MF_REG_RX_DATA_CTRL 0x00000050
/* [0x54]: REG rx data reg1 */
#define MF_REG_RX_DATA_REG1 0x00000054
/* [0x58]: REG rx data reg2 */
#define MF_REG_RX_DATA_REG2 0x00000058
/* [0x5c]: REG rx data reg3 */
#define MF_REG_RX_DATA_REG3 0x0000005c
/* [0x60]: REG rx data reg4 */
#define MF_REG_RX_DATA_REG4 0x00000060
/* [0x64]: REG rx data reg5 */
#define MF_REG_RX_DATA_REG5 0x00000064
/* [0x68]: REG rx data reg6 */
#define MF_REG_RX_DATA_REG6 0x00000068
/* [0x6c]: REG rx data reg7 */
#define MF_REG_RX_DATA_REG7 0x0000006c
/* [0x70]: REG rx data reg8 */
#define MF_REG_RX_DATA_REG8 0x00000070
/* [0x74]: REG rx data reg9 */
#define MF_REG_RX_DATA_REG9 0x00000074
/* [0x78]: REG rx data reg10 */
#define MF_REG_RX_DATA_REG10 0x00000078
/* [0x7c]: REG rx data reg11 */
#define MF_REG_RX_DATA_REG11 0x0000007c
/* [0x80]: REG rx data reg12 */
#define MF_REG_RX_DATA_REG12 0x00000080
/* [0x84]: REG rx data reg13 */
#define MF_REG_RX_DATA_REG13 0x00000084
/* [0x88]: REG rx data reg14 */
#define MF_REG_RX_DATA_REG14 0x00000088
/* [0x8c]: REG rx data reg15 */
#define MF_REG_RX_DATA_REG15 0x0000008c
/* [0x90]: REG rx data reg16 */
#define MF_REG_RX_DATA_REG16 0x00000090
/* [0x94]: REG rx data reg17 */
#define MF_REG_RX_DATA_REG17 0x00000094
/* [0x98]: REG rx data reg18 */
#define MF_REG_RX_DATA_REG18 0x00000098
/* [0x9c]: REG rx data reg19 */
#define MF_REG_RX_DATA_REG19 0x0000009c
/* [0xa0]: REG rx data reg20 */
#define MF_REG_RX_DATA_REG20 0x000000a0
/* [0xa4]: REG rx data reg21 */
#define MF_REG_RX_DATA_REG21 0x000000a4
/* [0xa8]: REG rx data reg22 */
#define MF_REG_RX_DATA_REG22 0x000000a8
/* [0xac]: REG rx data reg23 */
#define MF_REG_RX_DATA_REG23 0x000000ac
/* [0xb0]: REG rx data reg24 */
#define MF_REG_RX_DATA_REG24 0x000000b0
/* [0xb4]: REG rx data reg25 */
#define MF_REG_RX_DATA_REG25 0x000000b4
/* [0xb8]: REG rx data reg26 */
#define MF_REG_RX_DATA_REG26 0x000000b8
/* [0xbc]: REG rx data reg27 */
#define MF_REG_RX_DATA_REG27 0x000000bc
/* [0xc0]: REG rx data reg28 */
#define MF_REG_RX_DATA_REG28 0x000000c0
/* [0xc4]: REG rx data reg29 */
#define MF_REG_RX_DATA_REG29 0x000000c4
/* [0xc8]: REG rx data reg30 */
#define MF_REG_RX_DATA_REG30 0x000000c8
/* [0xcc]: REG rx data reg31 */
#define MF_REG_RX_DATA_REG31 0x000000cc
/* [0xd0]: REG rx data reg32 */
#define MF_REG_RX_DATA_REG32 0x000000d0
/* [0xd4]: REG rx data reg33 */
#define MF_REG_RX_DATA_REG33 0x000000d4
/* [0xd8]: REG rx data reg34 */
#define MF_REG_RX_DATA_REG34 0x000000d8
/* [0xdc]: REG rx data reg35 */
#define MF_REG_RX_DATA_REG35 0x000000dc
/* [0xe0]: REG rx data reg36 */
#define MF_REG_RX_DATA_REG36 0x000000e0
/* [0xe4]: REG rx data reg37 */
#define MF_REG_RX_DATA_REG37 0x000000e4
/* [0xe8]: REG rx data reg38 */
#define MF_REG_RX_DATA_REG38 0x000000e8
/* [0xec]: REG rx data reg39 */
#define MF_REG_RX_DATA_REG39 0x000000ec
/* [0xf0]: REG rx data reg40 */
#define MF_REG_RX_DATA_REG40 0x000000f0
/* [0xf4]: REG rx data reg41 */
#define MF_REG_RX_DATA_REG41 0x000000f4
/* [0xf8]: REG rx data reg42 */
#define MF_REG_RX_DATA_REG42 0x000000f8
/* [0xfc]: REG rx data reg43 */
#define MF_REG_RX_DATA_REG43 0x000000fc
/* [0x100]: REG rx data reg44 */
#define MF_REG_RX_DATA_REG44 0x00000100
/* [0x104]: REG rx data reg45 */
#define MF_REG_RX_DATA_REG45 0x00000104
/* [0x108]: REG rx data reg46 */
#define MF_REG_RX_DATA_REG46 0x00000108
/* [0x10c]: REG rx data reg47 */
#define MF_REG_RX_DATA_REG47 0x0000010c
/* [0x110]: REG rx data reg48 */
#define MF_REG_RX_DATA_REG48 0x00000110
/* [0x114]: REG rx data reg49 */
#define MF_REG_RX_DATA_REG49 0x00000114
/* [0x118]: REG rx data reg50 */
#define MF_REG_RX_DATA_REG50 0x00000118
/* [0x11c]: REG rx data reg51 */
#define MF_REG_RX_DATA_REG51 0x0000011c
/* [0x120]: REG rx data reg52 */
#define MF_REG_RX_DATA_REG52 0x00000120
/* [0x124]: REG rx data reg53 */
#define MF_REG_RX_DATA_REG53 0x00000124
/* [0x128]: REG rx data reg54 */
#define MF_REG_RX_DATA_REG54 0x00000128
/* [0x12c]: REG rx data reg55 */
#define MF_REG_RX_DATA_REG55 0x0000012c
/* [0x130]: REG rx data reg56 */
#define MF_REG_RX_DATA_REG56 0x00000130
/* [0x134]: REG rx data reg57 */
#define MF_REG_RX_DATA_REG57 0x00000134
/* [0x138]: REG rx data reg58 */
#define MF_REG_RX_DATA_REG58 0x00000138
/* [0x13c]: REG rx data reg59 */
#define MF_REG_RX_DATA_REG59 0x0000013c
/* [0x140]: REG rx data reg60 */
#define MF_REG_RX_DATA_REG60 0x00000140
/* [0x144]: REG rx data reg61 */
#define MF_REG_RX_DATA_REG61 0x00000144
/* [0x148]: REG rx data reg62 */
#define MF_REG_RX_DATA_REG62 0x00000148
/* [0x14c]: REG rx data reg63 */
#define MF_REG_RX_DATA_REG63 0x0000014c
/* [0x150]: REG rx data reg64 */
#define MF_REG_RX_DATA_REG64 0x00000150
/* [0x154]: REG rx data reg65 */
#define MF_REG_RX_DATA_REG65 0x00000154
/* [0x158]: REG rx data reg66 */
#define MF_REG_RX_DATA_REG66 0x00000158
/* [0x15c]: REG tx ctrl byte */
#define MF_REG_TX_DATA_CTRL 0x0000015c
/* [0x160]: REG tx data reg1 */
#define MF_REG_TX_DATA_REG1 0x00000160
/* [0x164]: REG tx data reg2 */
#define MF_REG_TX_DATA_REG2 0x00000164
/* [0x168]: REG tx data reg3 */
#define MF_REG_TX_DATA_REG3 0x00000168
/* [0x16c]: REG tx data reg4 */
#define MF_REG_TX_DATA_REG4 0x0000016c
/* [0x170]: REG tx data reg5 */
#define MF_REG_TX_DATA_REG5 0x00000170
/* [0x174]: REG tx data reg6 */
#define MF_REG_TX_DATA_REG6 0x00000174
/* [0x178]: REG tx data reg7 */
#define MF_REG_TX_DATA_REG7 0x00000178
/* [0x17c]: REG tx data reg8 */
#define MF_REG_TX_DATA_REG8 0x0000017c
/* [0x180]: REG tx data reg9 */
#define MF_REG_TX_DATA_REG9 0x00000180
/* [0x184]: REG tx data reg10 */
#define MF_REG_TX_DATA_REG10 0x00000184
/* [0x188]: REG tx data reg11 */
#define MF_REG_TX_DATA_REG11 0x00000188
/* [0x18c]: REG tx data reg12 */
#define MF_REG_TX_DATA_REG12 0x0000018c
/* [0x190]: REG tx data reg13 */
#define MF_REG_TX_DATA_REG13 0x00000190
/* [0x194]: REG tx data reg14 */
#define MF_REG_TX_DATA_REG14 0x00000194
/* [0x198]: REG tx data reg15 */
#define MF_REG_TX_DATA_REG15 0x00000198
/* [0x19c]: REG tx data reg16 */
#define MF_REG_TX_DATA_REG16 0x0000019c
/* [0x1a0]: REG tx data reg17 */
#define MF_REG_TX_DATA_REG17 0x000001a0
/* [0x1a4]: REG tx data reg18 */
#define MF_REG_TX_DATA_REG18 0x000001a4
/* [0x1a8]: REG tx data reg19 */
#define MF_REG_TX_DATA_REG19 0x000001a8
/* [0x1ac]: REG tx data reg20 */
#define MF_REG_TX_DATA_REG20 0x000001ac
/* [0x1b0]: REG tx data reg21 */
#define MF_REG_TX_DATA_REG21 0x000001b0
/* [0x1b4]: REG tx data reg22 */
#define MF_REG_TX_DATA_REG22 0x000001b4
/* [0x1b8]: REG tx data reg23 */
#define MF_REG_TX_DATA_REG23 0x000001b8
/* [0x1bc]: REG tx data reg24 */
#define MF_REG_TX_DATA_REG24 0x000001bc
/* [0x1c0]: REG tx data reg25 */
#define MF_REG_TX_DATA_REG25 0x000001c0
/* [0x1c4]: REG tx data reg26 */
#define MF_REG_TX_DATA_REG26 0x000001c4
/* [0x1c8]: REG tx data reg27 */
#define MF_REG_TX_DATA_REG27 0x000001c8
/* [0x1cc]: REG tx data reg28 */
#define MF_REG_TX_DATA_REG28 0x000001cc
/* [0x1d0]: REG tx data reg29 */
#define MF_REG_TX_DATA_REG29 0x000001d0
/* [0x1d4]: REG tx data reg30 */
#define MF_REG_TX_DATA_REG30 0x000001d4
/* [0x1d8]: REG tx data reg31 */
#define MF_REG_TX_DATA_REG31 0x000001d8
/* [0x1dc]: REG tx data reg32 */
#define MF_REG_TX_DATA_REG32 0x000001dc
/* [0x1e0]: REG tx data reg33 */
#define MF_REG_TX_DATA_REG33 0x000001e0
/* [0x1e4]: REG tx data reg34 */
#define MF_REG_TX_DATA_REG34 0x000001e4
/* [0x1e8]: REG tx data reg35 */
#define MF_REG_TX_DATA_REG35 0x000001e8
/* [0x1ec]: REG tx data reg36 */
#define MF_REG_TX_DATA_REG36 0x000001ec
/* [0x1f0]: REG tx data reg37 */
#define MF_REG_TX_DATA_REG37 0x000001f0
/* [0x1f4]: REG tx data reg38 */
#define MF_REG_TX_DATA_REG38 0x000001f4
/* [0x1f8]: REG tx data reg39 */
#define MF_REG_TX_DATA_REG39 0x000001f8
/* [0x1fc]: REG tx data reg40 */
#define MF_REG_TX_DATA_REG40 0x000001fc
/* [0x200]: REG tx data reg41 */
#define MF_REG_TX_DATA_REG41 0x00000200
/* [0x204]: REG tx data reg42 */
#define MF_REG_TX_DATA_REG42 0x00000204
/* [0x208]: REG tx data reg43 */
#define MF_REG_TX_DATA_REG43 0x00000208
/* [0x20c]: REG tx data reg44 */
#define MF_REG_TX_DATA_REG44 0x0000020c
/* [0x210]: REG tx data reg45 */
#define MF_REG_TX_DATA_REG45 0x00000210
/* [0x214]: REG tx data reg46 */
#define MF_REG_TX_DATA_REG46 0x00000214
/* [0x218]: REG tx data reg47 */
#define MF_REG_TX_DATA_REG47 0x00000218
/* [0x21c]: REG tx data reg48 */
#define MF_REG_TX_DATA_REG48 0x0000021c
/* [0x220]: REG tx data reg49 */
#define MF_REG_TX_DATA_REG49 0x00000220
/* [0x224]: REG tx data reg50 */
#define MF_REG_TX_DATA_REG50 0x00000224
/* [0x228]: REG tx data reg51 */
#define MF_REG_TX_DATA_REG51 0x00000228
/* [0x22c]: REG tx data reg52 */
#define MF_REG_TX_DATA_REG52 0x0000022c
/* [0x230]: REG tx data reg53 */
#define MF_REG_TX_DATA_REG53 0x00000230
/* [0x234]: REG tx data reg54 */
#define MF_REG_TX_DATA_REG54 0x00000234
/* [0x238]: REG tx data reg55 */
#define MF_REG_TX_DATA_REG55 0x00000238
/* [0x23c]: REG tx data reg56 */
#define MF_REG_TX_DATA_REG56 0x0000023c
/* [0x240]: REG tx data reg57 */
#define MF_REG_TX_DATA_REG57 0x00000240
/* [0x244]: REG tx data reg58 */
#define MF_REG_TX_DATA_REG58 0x00000244
/* [0x248]: REG tx data reg59 */
#define MF_REG_TX_DATA_REG59 0x00000248
/* [0x24c]: REG tx data reg60 */
#define MF_REG_TX_DATA_REG60 0x0000024c
/* [0x250]: REG tx data reg61 */
#define MF_REG_TX_DATA_REG61 0x00000250
/* [0x254]: REG tx data reg62 */
#define MF_REG_TX_DATA_REG62 0x00000254
/* [0x258]: REG tx data reg63 */
#define MF_REG_TX_DATA_REG63 0x00000258
/* [0x25c]: REG tx data reg64 */
#define MF_REG_TX_DATA_REG64 0x0000025c
/* [0x260]: REG tx data reg65 */
#define MF_REG_TX_DATA_REG65 0x00000260
/* [0x264]: REG tx data reg66 */
#define MF_REG_TX_DATA_REG66 0x00000264
/* [0x18]: REG bus speed */
#define MF_REG_SPEED 0x00000018
/* [0x1c]: REG macrocycle lgth */
#define MF_REG_MACROCYC 0x0000001c
/* [0x20]: REG turnaround lgth */
#define MF_REG_TURNAR 0x00000020
/* [0x24]: REG silence lgth */
#define MF_REG_SILEN 0x00000024
/* [0x28]: REG macrocycle time cnt */
#define MF_REG_MACROCYC_TIME_CNT 0x00000028
/* [0x2c]: REG macrocycles number cnt */
#define MF_REG_MACROCYC_NUM_CNT 0x0000002c
/* [0x30]: REG turnaround time cnt */
#define MF_REG_TURNAR_TIME_CNT 0x00000030
/* [0x34]: REG silence time cnt */
#define MF_REG_SILEN_TIME_CNT 0x00000034
/* [0x38]: REG tx ctrl */
#define MF_REG_TX_CTRL 0x00000038
/* [0x3c]: REG tx status */
#define MF_REG_TX_STAT 0x0000003c
/* [0x40]: REG fieldrive wdgn */
#define MF_REG_FD_WDGN 0x00000040
/* [0x44]: REG fieldrive txer cnt */
#define MF_REG_FD_TXER_CNT 0x00000044
/* [0x48]: REG fieldrive txer tstamp */
#define MF_REG_FD_TXER_TSTAMP 0x00000048
/* [0x4c]: REG rx ctrl */
#define MF_REG_RX_CTRL 0x0000004c
/* [0x50]: REG rx status */
#define MF_REG_RX_STAT 0x00000050
/* [0x54]: REG rx status current byte index */
#define MF_REG_RX_STAT_CURR_BYTE_INDX 0x00000054
/* [0x58]: REG rx data ctrl byte */
#define MF_REG_RX_DATA_CTRL 0x00000058
/* [0x5c]: REG rx data reg1 */
#define MF_REG_RX_DATA_REG1 0x0000005c
/* [0x60]: REG rx data reg2 */
#define MF_REG_RX_DATA_REG2 0x00000060
/* [0x64]: REG rx data reg3 */
#define MF_REG_RX_DATA_REG3 0x00000064
/* [0x68]: REG rx data reg4 */
#define MF_REG_RX_DATA_REG4 0x00000068
/* [0x6c]: REG rx data reg5 */
#define MF_REG_RX_DATA_REG5 0x0000006c
/* [0x70]: REG rx data reg6 */
#define MF_REG_RX_DATA_REG6 0x00000070
/* [0x74]: REG rx data reg7 */
#define MF_REG_RX_DATA_REG7 0x00000074
/* [0x78]: REG rx data reg8 */
#define MF_REG_RX_DATA_REG8 0x00000078
/* [0x7c]: REG rx data reg9 */
#define MF_REG_RX_DATA_REG9 0x0000007c
/* [0x80]: REG rx data reg10 */
#define MF_REG_RX_DATA_REG10 0x00000080
/* [0x84]: REG rx data reg11 */
#define MF_REG_RX_DATA_REG11 0x00000084
/* [0x88]: REG rx data reg12 */
#define MF_REG_RX_DATA_REG12 0x00000088
/* [0x8c]: REG rx data reg13 */
#define MF_REG_RX_DATA_REG13 0x0000008c
/* [0x90]: REG rx data reg14 */
#define MF_REG_RX_DATA_REG14 0x00000090
/* [0x94]: REG rx data reg15 */
#define MF_REG_RX_DATA_REG15 0x00000094
/* [0x98]: REG rx data reg16 */
#define MF_REG_RX_DATA_REG16 0x00000098
/* [0x9c]: REG rx data reg17 */
#define MF_REG_RX_DATA_REG17 0x0000009c
/* [0xa0]: REG rx data reg18 */
#define MF_REG_RX_DATA_REG18 0x000000a0
/* [0xa4]: REG rx data reg19 */
#define MF_REG_RX_DATA_REG19 0x000000a4
/* [0xa8]: REG rx data reg20 */
#define MF_REG_RX_DATA_REG20 0x000000a8
/* [0xac]: REG rx data reg21 */
#define MF_REG_RX_DATA_REG21 0x000000ac
/* [0xb0]: REG rx data reg22 */
#define MF_REG_RX_DATA_REG22 0x000000b0
/* [0xb4]: REG rx data reg23 */
#define MF_REG_RX_DATA_REG23 0x000000b4
/* [0xb8]: REG rx data reg24 */
#define MF_REG_RX_DATA_REG24 0x000000b8
/* [0xbc]: REG rx data reg25 */
#define MF_REG_RX_DATA_REG25 0x000000bc
/* [0xc0]: REG rx data reg26 */
#define MF_REG_RX_DATA_REG26 0x000000c0
/* [0xc4]: REG rx data reg27 */
#define MF_REG_RX_DATA_REG27 0x000000c4
/* [0xc8]: REG rx data reg28 */
#define MF_REG_RX_DATA_REG28 0x000000c8
/* [0xcc]: REG rx data reg29 */
#define MF_REG_RX_DATA_REG29 0x000000cc
/* [0xd0]: REG rx data reg30 */
#define MF_REG_RX_DATA_REG30 0x000000d0
/* [0xd4]: REG rx data reg31 */
#define MF_REG_RX_DATA_REG31 0x000000d4
/* [0xd8]: REG rx data reg32 */
#define MF_REG_RX_DATA_REG32 0x000000d8
/* [0xdc]: REG rx data reg33 */
#define MF_REG_RX_DATA_REG33 0x000000dc
/* [0xe0]: REG rx data reg34 */
#define MF_REG_RX_DATA_REG34 0x000000e0
/* [0xe4]: REG rx data reg35 */
#define MF_REG_RX_DATA_REG35 0x000000e4
/* [0xe8]: REG rx data reg36 */
#define MF_REG_RX_DATA_REG36 0x000000e8
/* [0xec]: REG rx data reg37 */
#define MF_REG_RX_DATA_REG37 0x000000ec
/* [0xf0]: REG rx data reg38 */
#define MF_REG_RX_DATA_REG38 0x000000f0
/* [0xf4]: REG rx data reg39 */
#define MF_REG_RX_DATA_REG39 0x000000f4
/* [0xf8]: REG rx data reg40 */
#define MF_REG_RX_DATA_REG40 0x000000f8
/* [0xfc]: REG rx data reg41 */
#define MF_REG_RX_DATA_REG41 0x000000fc
/* [0x100]: REG rx data reg42 */
#define MF_REG_RX_DATA_REG42 0x00000100
/* [0x104]: REG rx data reg43 */
#define MF_REG_RX_DATA_REG43 0x00000104
/* [0x108]: REG rx data reg44 */
#define MF_REG_RX_DATA_REG44 0x00000108
/* [0x10c]: REG rx data reg45 */
#define MF_REG_RX_DATA_REG45 0x0000010c
/* [0x110]: REG rx data reg46 */
#define MF_REG_RX_DATA_REG46 0x00000110
/* [0x114]: REG rx data reg47 */
#define MF_REG_RX_DATA_REG47 0x00000114
/* [0x118]: REG rx data reg48 */
#define MF_REG_RX_DATA_REG48 0x00000118
/* [0x11c]: REG rx data reg49 */
#define MF_REG_RX_DATA_REG49 0x0000011c
/* [0x120]: REG rx data reg50 */
#define MF_REG_RX_DATA_REG50 0x00000120
/* [0x124]: REG rx data reg51 */
#define MF_REG_RX_DATA_REG51 0x00000124
/* [0x128]: REG rx data reg52 */
#define MF_REG_RX_DATA_REG52 0x00000128
/* [0x12c]: REG rx data reg53 */
#define MF_REG_RX_DATA_REG53 0x0000012c
/* [0x130]: REG rx data reg54 */
#define MF_REG_RX_DATA_REG54 0x00000130
/* [0x134]: REG rx data reg55 */
#define MF_REG_RX_DATA_REG55 0x00000134
/* [0x138]: REG rx data reg56 */
#define MF_REG_RX_DATA_REG56 0x00000138
/* [0x13c]: REG rx data reg57 */
#define MF_REG_RX_DATA_REG57 0x0000013c
/* [0x140]: REG rx data reg58 */
#define MF_REG_RX_DATA_REG58 0x00000140
/* [0x144]: REG rx data reg59 */
#define MF_REG_RX_DATA_REG59 0x00000144
/* [0x148]: REG rx data reg60 */
#define MF_REG_RX_DATA_REG60 0x00000148
/* [0x14c]: REG rx data reg61 */
#define MF_REG_RX_DATA_REG61 0x0000014c
/* [0x150]: REG rx data reg62 */
#define MF_REG_RX_DATA_REG62 0x00000150
/* [0x154]: REG rx data reg63 */
#define MF_REG_RX_DATA_REG63 0x00000154
/* [0x158]: REG rx data reg64 */
#define MF_REG_RX_DATA_REG64 0x00000158
/* [0x15c]: REG rx data reg65 */
#define MF_REG_RX_DATA_REG65 0x0000015c
/* [0x160]: REG rx data reg66 */
#define MF_REG_RX_DATA_REG66 0x00000160
/* [0x164]: REG rx data reg67 */
#define MF_REG_RX_DATA_REG67 0x00000164
/* [0x168]: REG tx ctrl byte */
#define MF_REG_TX_DATA_CTRL 0x00000168
/* [0x16c]: REG tx data reg1 */
#define MF_REG_TX_DATA_REG1 0x0000016c
/* [0x170]: REG tx data reg2 */
#define MF_REG_TX_DATA_REG2 0x00000170
/* [0x174]: REG tx data reg3 */
#define MF_REG_TX_DATA_REG3 0x00000174
/* [0x178]: REG tx data reg4 */
#define MF_REG_TX_DATA_REG4 0x00000178
/* [0x17c]: REG tx data reg5 */
#define MF_REG_TX_DATA_REG5 0x0000017c
/* [0x180]: REG tx data reg6 */
#define MF_REG_TX_DATA_REG6 0x00000180
/* [0x184]: REG tx data reg7 */
#define MF_REG_TX_DATA_REG7 0x00000184
/* [0x188]: REG tx data reg8 */
#define MF_REG_TX_DATA_REG8 0x00000188
/* [0x18c]: REG tx data reg9 */
#define MF_REG_TX_DATA_REG9 0x0000018c
/* [0x190]: REG tx data reg10 */
#define MF_REG_TX_DATA_REG10 0x00000190
/* [0x194]: REG tx data reg11 */
#define MF_REG_TX_DATA_REG11 0x00000194
/* [0x198]: REG tx data reg12 */
#define MF_REG_TX_DATA_REG12 0x00000198
/* [0x19c]: REG tx data reg13 */
#define MF_REG_TX_DATA_REG13 0x0000019c
/* [0x1a0]: REG tx data reg14 */
#define MF_REG_TX_DATA_REG14 0x000001a0
/* [0x1a4]: REG tx data reg15 */
#define MF_REG_TX_DATA_REG15 0x000001a4
/* [0x1a8]: REG tx data reg16 */
#define MF_REG_TX_DATA_REG16 0x000001a8
/* [0x1ac]: REG tx data reg17 */
#define MF_REG_TX_DATA_REG17 0x000001ac
/* [0x1b0]: REG tx data reg18 */
#define MF_REG_TX_DATA_REG18 0x000001b0
/* [0x1b4]: REG tx data reg19 */
#define MF_REG_TX_DATA_REG19 0x000001b4
/* [0x1b8]: REG tx data reg20 */
#define MF_REG_TX_DATA_REG20 0x000001b8
/* [0x1bc]: REG tx data reg21 */
#define MF_REG_TX_DATA_REG21 0x000001bc
/* [0x1c0]: REG tx data reg22 */
#define MF_REG_TX_DATA_REG22 0x000001c0
/* [0x1c4]: REG tx data reg23 */
#define MF_REG_TX_DATA_REG23 0x000001c4
/* [0x1c8]: REG tx data reg24 */
#define MF_REG_TX_DATA_REG24 0x000001c8
/* [0x1cc]: REG tx data reg25 */
#define MF_REG_TX_DATA_REG25 0x000001cc
/* [0x1d0]: REG tx data reg26 */
#define MF_REG_TX_DATA_REG26 0x000001d0
/* [0x1d4]: REG tx data reg27 */
#define MF_REG_TX_DATA_REG27 0x000001d4
/* [0x1d8]: REG tx data reg28 */
#define MF_REG_TX_DATA_REG28 0x000001d8
/* [0x1dc]: REG tx data reg29 */
#define MF_REG_TX_DATA_REG29 0x000001dc
/* [0x1e0]: REG tx data reg30 */
#define MF_REG_TX_DATA_REG30 0x000001e0
/* [0x1e4]: REG tx data reg31 */
#define MF_REG_TX_DATA_REG31 0x000001e4
/* [0x1e8]: REG tx data reg32 */
#define MF_REG_TX_DATA_REG32 0x000001e8
/* [0x1ec]: REG tx data reg33 */
#define MF_REG_TX_DATA_REG33 0x000001ec
/* [0x1f0]: REG tx data reg34 */
#define MF_REG_TX_DATA_REG34 0x000001f0
/* [0x1f4]: REG tx data reg35 */
#define MF_REG_TX_DATA_REG35 0x000001f4
/* [0x1f8]: REG tx data reg36 */
#define MF_REG_TX_DATA_REG36 0x000001f8
/* [0x1fc]: REG tx data reg37 */
#define MF_REG_TX_DATA_REG37 0x000001fc
/* [0x200]: REG tx data reg38 */
#define MF_REG_TX_DATA_REG38 0x00000200
/* [0x204]: REG tx data reg39 */
#define MF_REG_TX_DATA_REG39 0x00000204
/* [0x208]: REG tx data reg40 */
#define MF_REG_TX_DATA_REG40 0x00000208
/* [0x20c]: REG tx data reg41 */
#define MF_REG_TX_DATA_REG41 0x0000020c
/* [0x210]: REG tx data reg42 */
#define MF_REG_TX_DATA_REG42 0x00000210
/* [0x214]: REG tx data reg43 */
#define MF_REG_TX_DATA_REG43 0x00000214
/* [0x218]: REG tx data reg44 */
#define MF_REG_TX_DATA_REG44 0x00000218
/* [0x21c]: REG tx data reg45 */
#define MF_REG_TX_DATA_REG45 0x0000021c
/* [0x220]: REG tx data reg46 */
#define MF_REG_TX_DATA_REG46 0x00000220
/* [0x224]: REG tx data reg47 */
#define MF_REG_TX_DATA_REG47 0x00000224
/* [0x228]: REG tx data reg48 */
#define MF_REG_TX_DATA_REG48 0x00000228
/* [0x22c]: REG tx data reg49 */
#define MF_REG_TX_DATA_REG49 0x0000022c
/* [0x230]: REG tx data reg50 */
#define MF_REG_TX_DATA_REG50 0x00000230
/* [0x234]: REG tx data reg51 */
#define MF_REG_TX_DATA_REG51 0x00000234
/* [0x238]: REG tx data reg52 */
#define MF_REG_TX_DATA_REG52 0x00000238
/* [0x23c]: REG tx data reg53 */
#define MF_REG_TX_DATA_REG53 0x0000023c
/* [0x240]: REG tx data reg54 */
#define MF_REG_TX_DATA_REG54 0x00000240
/* [0x244]: REG tx data reg55 */
#define MF_REG_TX_DATA_REG55 0x00000244
/* [0x248]: REG tx data reg56 */
#define MF_REG_TX_DATA_REG56 0x00000248
/* [0x24c]: REG tx data reg57 */
#define MF_REG_TX_DATA_REG57 0x0000024c
/* [0x250]: REG tx data reg58 */
#define MF_REG_TX_DATA_REG58 0x00000250
/* [0x254]: REG tx data reg59 */
#define MF_REG_TX_DATA_REG59 0x00000254
/* [0x258]: REG tx data reg60 */
#define MF_REG_TX_DATA_REG60 0x00000258
/* [0x25c]: REG tx data reg61 */
#define MF_REG_TX_DATA_REG61 0x0000025c
/* [0x260]: REG tx data reg62 */
#define MF_REG_TX_DATA_REG62 0x00000260
/* [0x264]: REG tx data reg63 */
#define MF_REG_TX_DATA_REG63 0x00000264
/* [0x268]: REG tx data reg64 */
#define MF_REG_TX_DATA_REG64 0x00000268
/* [0x26c]: REG tx data reg65 */
#define MF_REG_TX_DATA_REG65 0x0000026c
/* [0x270]: REG tx data reg66 */
#define MF_REG_TX_DATA_REG66 0x00000270
/* [0x274]: REG tx data reg67 */
#define MF_REG_TX_DATA_REG67 0x00000274
#endif
rtl/wbgen/fmc_masterfip_csr.htm
View file @ 9aa29601
This source diff could not be displayed because it is too large. You can view the blob instead.
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 9aa29601
......@@ -222,7 +222,10 @@ peripheral {
field {
name = "speed";
description = "WorldFIP speed: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: 5 Mbps";
description = "WorldFIP speed: 00: 31.25Kbps\
01: 1Mbps\
10: 2.5 Mbps\
11: 5 Mbps";
type = SLV;
size = 2;
access_bus = READ_ONLY;
......@@ -394,7 +397,7 @@ peripheral {
note that the max WorldFIP frame size = 263 bytes (without preamble, CRC, postamble)";
prefix = "bytes_num";
type = SLV;
size = 9;
size = 16;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -411,25 +414,14 @@ peripheral {
field {
name = "tx ended";
description = "indication that the serializer finished the delivery of a frame";
description = "indication that the serializer finished the delivery of a frame\
the bit stays active until a rstn_core or a tx_ctrl_rst or a tx_ctrl_strt";
prefix = "stop";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx current byte";
description = "index of the byte currently being serialized.\
note that the max WorldFIP frame size = 263 bytes (without preamble, CRC, postamble)";
prefix = "byte_index";
type = SLV;
size = 9;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx enable";
description = "fieldrive fd_txena signal;\
......@@ -441,37 +433,85 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx status current byte index";
description = "index of the current byte being serialized;\
the counting starts from 0 after the preamble...";
prefix = "curr_byte_indx";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
-- fieldrive status signals --
-------------------------------------------------------------------------------
reg {
name = "fieldrive status";
prefix = "fd";
name = "fieldrive wdgn";
prefix = "fd_wdgn";
field {
name = "fd watchdog";
description = "fd_wdgn input from the fieldrive chip\
read 0: no problemo i think\
read 1: something 's wrong...";
prefix = "wdgn";
type = BIT;
name = "fd_wdgn_tstamp";
description = "timestamp of the moment in the macrocycle when the fd_wdgn\
was activated.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
prefix = "tstamp";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "fd transmitter error";
description = "fd_txer input from the fieldrive chip\
read 0: no problemo i think\
read 1: something 's wrong...";
prefix = "txer";
name = "fd_wdg_act";
description = "read 1: the fd_wdgn has been activated\
read 0: no problemo\
Note that if triggered, the fd_wdgn stays active until a fd_rstn";
prefix = "act";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
reg {
name = "fieldrive txer cnt";
prefix = "fd_txer_cnt";
field {
name = "fd_txer_cnt";
description = "counter of the number of fd_txer rising edges that appear in this\
current macrocycle.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "fieldrive txer tstamp";
prefix = "fd_txer_tstamp";
field {
name = "fd_txer_tstamp";
description = "timestamp of the last moment in the macrocycle when the fd_txer\
was activated.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
-- deserializer ctrl --
......@@ -504,8 +544,9 @@ peripheral {
field {
name = "rx preamble detected";
description = "indication that the deserializer has detected a preamble;\
the bit stays high until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a mf_rx_ctrl_rst)";
the bit stays active until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a rx_ctrl_rst\
or upon a core_rstn)";
prefix = "pream_ok";
type = BIT;
access_bus = READ_ONLY;
......@@ -517,7 +558,8 @@ peripheral {
description = "indication that the deserializer has finished with the reception of a complete frame;\
the preamble, CRC and postambe of the frame are all ok\
the bit stays high until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a rx_rst)";
automatically upon the activation of the serializer, or upon a rx_ctrl_rst\
or upon a rstn_core)";
prefix = "frame_ok";
type = BIT;
access_bus = READ_ONLY;
......
sim/spec/data_vectors/masterFIP_test.vec
View file @ 9aa29601
......@@ -60,101 +60,101 @@ wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030038 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003015C F 00000003
wr 0000000000030160 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030160 F 00000305
wr 0000000000030164 F 00000305
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030038 F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030038 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
wait %d20
-- control byte of rp_dat
wr 000000000003015C F 00000002
wr 0000000000030160 F 00000002
wait %d20
-- data bytes
wr 0000000000030160 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wr 0000000000030164 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wr 000000000003015c F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wr 0000000000030168 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
-- tx_start
wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wr 0000000000030038 F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wait %d40000
--------------- ID_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030038 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003015C F 00000003
wr 0000000000030160 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030160 F 00000314
wr 0000000000030164 F 00000314
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030038 F 00000202
wait %d20
-- deactivate tx_start
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wr 0000000000030044 F 00000000
wait %d40000
-- read received data
rd 0000000000030050 F 00000002
wait %d20
rd 000000000003004c F 03800550
rd 0000000000030044 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 000000000003003C F 00000001
wr 0000000000030038 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003015C F 00000003
wr 0000000000030160 F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030160 F 00000306
wr 0000000000030164 F 00000306
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030038 F 00000202
wait %d20
-- deactivate tx_start
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wr 0000000000030044 F 00000000
wait %d40000
-- read received data
......@@ -244,5 +244,5 @@ wr 0000000000030048 F 00000001
wait %d20
-- tx_start
wr 000000000003003C F 00000002
wr 0000000000030038 F 00000002
wait %d20000
\ No newline at end of file
sim/spec/data_vectors/user_logic_config.txt
View file @ 9aa29601
10 ns -- User clock period (should not be modified during test)
10 ns -- Wishbone interface clock period (should not be modified during test)
25 ns -- User clock period (should not be modified during test)
25 ns -- Wishbone interface clock period (should not be modified during test)
3 us -- Power-on reset length
1 us -- User reset length
1 us -- Wishbone interface reset length
20000 ms -- validity time: time for which the configuration above is valid
20000 ms -- validity time: time for which the configuration above is valid
sim/spec/testbench/nanoFIP/dualram_512x8.vhd → sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd
View file @ 9aa29601
......@@ -52,12 +52,9 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.gencores_pkg.all;
use work.genram_pkg.all;
-- Component specific library
--library PROASIC3; -- ProASIC3 library
--use PROASIC3.all;
library PROASIC3; -- ProASIC3 library
use PROASIC3.all;
--=================================================================================================
......@@ -124,227 +121,166 @@ architecture RAM4K9 of dualram_512x8 is
-- A Low on this signal makes the output retain data from the previous Read. A High indicates a
-- pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
generic (MEMORYFILE : string := "");
port(
ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0,
ADDRB11, ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6,
ADDRB5, ADDRB4, ADDRB3, ADDRB2, ADDRB1, ADDRB0,
DINA8, DINA7, DINA6, DINA5, DINA4, DINA3, DINA2, DINA1, DINA0,
DINB8, DINB7, DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0,
WIDTHA0, WIDTHA1,
WIDTHB0, WIDTHB1,
PIPEA, PIPEB,
WMODEA, WMODEB,
BLKA, BLKB,
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic := 'U';
----------------------------------------------------
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic);
----------------------------------------------------
end component;
-- component RAM4K9
-- generic (MEMORYFILE : string := "");
-- port(
-- ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
-- ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0,
-- ADDRB11, ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6,
-- ADDRB5, ADDRB4, ADDRB3, ADDRB2, ADDRB1, ADDRB0,
-- DINA8, DINA7, DINA6, DINA5, DINA4, DINA3, DINA2, DINA1, DINA0,
-- DINB8, DINB7, DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0,
-- WIDTHA0, WIDTHA1,
-- WIDTHB0, WIDTHB1,
-- PIPEA, PIPEB,
-- WMODEA, WMODEB,
-- BLKA, BLKB,
-- WENA, WENB,
-- CLKA, CLKB,
-- RESET : in std_logic := 'U';
-- ----------------------------------------------------
-- DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
-- DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic);
-- ----------------------------------------------------
-- end component;
component generic_dpram_dualclock
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
---------------------------------------------------------------------------------------------------
-- Instantiation of the component VCC
--component VCCtmp
-- port (Y : out std_logic);
--end component;
component VCC
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
-- Instantiation of the component GND
--component GNDtmp
-- port (Y : out std_logic);
--end component;
component GND
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
--signal POWER, GROUND : std_logic;
signal wea, web : std_logic;
signal POWER, GROUND : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
wea <= not RWA;
web <= not RWB;
--power_supply_signal : VCCtmp port map(Y => POWER);
--ground_signal : GNDtmp port map(Y => GROUND);
power_supply_signal : VCC port map(Y => POWER);
ground_signal : GND port map(Y => GROUND);
---------------------------------------------------------------------------------------------------
-- Instantiation of the component RAM4K9.
-- The following configuration has been applied:
-- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCCtmp)
-- o word width : 8 bits (DINA8, DINB8: GNDtmp; DOUTA8, DOUTB8 : open)
-- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GNDtmp)
-- o BLKA, BLKB : GNDtmp (ports enabled)
-- o PIPEA, PIPEB : GNDtmp (not pipelined read)
-- o WMODEA, WMODEB: GNDtmp (in write mode the output retains the data from the previous read)
DualClkRam : generic_dpram_dualclock
generic map (
g_data_width => 8,
g_size => 512)
port map (
rst_n_i =>'1',
-- Port A
clka_i => CLKA,
bwea_i => "1",
wea_i => wea,
aa_i => ADDRA,
da_i => DINA,
qa_o => DOUTA,
-- Port B
clkb_i => CLKB,
bweb_i => "1",
web_i => web,
ab_i => ADDRB,
db_i => DINB,
qb_o => DOUTB);
-- A9D8DualClkRAM_R0C0 : RAM4K9
-- port map(
-- -- INPUTS
-- -- inputs concerning port A
-- -- data in A (1 byte, (7 downto 0))
-- DINA8 => GROUND,
-- DINA7 => DINA(7),
-- DINA6 => DINA(6),
-- DINA5 => DINA(5),
-- DINA4 => DINA(4),
-- DINA3 => DINA(3),
-- DINA2 => DINA(2),
-- DINA1 => DINA(1),
-- DINA0 => DINA(0),
-- -- address A (512 bytes depth, (8 downto 0))
-- ADDRA11 => GROUND,
-- ADDRA10 => GROUND,
-- ADDRA9 => GROUND,
-- ADDRA8 => ADDRA(8),
-- ADDRA7 => ADDRA(7),
-- ADDRA6 => ADDRA(6),
-- ADDRA5 => ADDRA(5),
-- ADDRA4 => ADDRA(4),
-- ADDRA3 => ADDRA(3),
-- ADDRA2 => ADDRA(2),
-- ADDRA1 => ADDRA(1),
-- ADDRA0 => ADDRA(0),
-- -- read/ write mode for A
-- WENA => RWA,
-- -- clock for A
-- CLKA => CLKA,
-- -- aspect ratio, block, pipeline, write mode configurations for port A
-- WIDTHA0 => POWER,
-- WIDTHA1 => POWER,
-- BLKA => GROUND,
-- PIPEA => GROUND,
-- WMODEA => GROUND,
-- -- inputs concerning port B
-- -- data in B (1 byte, (7 downto 0))
-- DINB8 => GROUND,
-- DINB7 => DINB(7),
-- DINB6 => DINB(6),
-- DINB5 => DINB(5),
-- DINB4 => DINB(4),
-- DINB3 => DINB(3),
-- DINB2 => DINB(2),
-- DINB1 => DINB(1),
-- DINB0 => DINB(0),
-- -- address B (512 bytes depth, (8 downto 0))
-- ADDRB11 => GROUND,
-- ADDRB10 => GROUND,
-- ADDRB9 => GROUND,
-- ADDRB8 => ADDRB(8),
-- ADDRB7 => ADDRB(7),
-- ADDRB6 => ADDRB(6),
-- ADDRB5 => ADDRB(5),
-- ADDRB4 => ADDRB(4),
-- ADDRB3 => ADDRB(3),
-- ADDRB2 => ADDRB(2),
-- ADDRB1 => ADDRB(1),
-- ADDRB0 => ADDRB(0),
-- -- read/ write mode for B
-- WENB => RWB,
-- -- clock for B
-- CLKB => CLKB,
-- -- aspect ratio, block, pipeline, write mode configurations for port B
-- WIDTHB0 => POWER,
-- WIDTHB1 => POWER,
-- BLKB => GROUND,
-- PIPEB => GROUND,
-- WMODEB => GROUND,
-- -- input reset
-- RESET => RESETn,
-- -------------------------------
-- -- OUTPUTS
-- -- output concerning port A
-- -- data out A (1 byte)
-- DOUTA8 => open,
-- DOUTA7 => DOUTA(7),
-- DOUTA6 => DOUTA(6),
-- DOUTA5 => DOUTA(5),
-- DOUTA4 => DOUTA(4),
-- DOUTA3 => DOUTA(3),
-- DOUTA2 => DOUTA(2),
-- DOUTA1 => DOUTA(1),
-- DOUTA0 => DOUTA(0),
-- -- output concerning port B
-- -- data out B (1 byte)
-- DOUTB8 => open,
-- DOUTB7 => DOUTB(7),
-- DOUTB6 => DOUTB(6),
-- DOUTB5 => DOUTB(5),
-- DOUTB4 => DOUTB(4),
-- DOUTB3 => DOUTB(3),
-- DOUTB2 => DOUTB(2),
-- DOUTB1 => DOUTB(1),
-- DOUTB0 => DOUTB(0));
-- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
-- o word width : 8 bits (DINA8, DINB8: GND; DOUTA8, DOUTB8 : open)
-- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GND)
-- o BLKA, BLKB : GND (ports enabled)
-- o PIPEA, PIPEB : GND (not pipelined read)
-- o WMODEA, WMODEB: GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
-- INPUTS
-- inputs concerning port A
-- data in A (1 byte, (7 downto 0))
DINA8 => GROUND,
DINA7 => DINA(7),
DINA6 => DINA(6),
DINA5 => DINA(5),
DINA4 => DINA(4),
DINA3 => DINA(3),
DINA2 => DINA(2),
DINA1 => DINA(1),
DINA0 => DINA(0),
-- address A (512 bytes depth, (8 downto 0))
ADDRA11 => GROUND,
ADDRA10 => GROUND,
ADDRA9 => GROUND,
ADDRA8 => ADDRA(8),
ADDRA7 => ADDRA(7),
ADDRA6 => ADDRA(6),
ADDRA5 => ADDRA(5),
ADDRA4 => ADDRA(4),
ADDRA3 => ADDRA(3),
ADDRA2 => ADDRA(2),
ADDRA1 => ADDRA(1),
ADDRA0 => ADDRA(0),
-- read/ write mode for A
WENA => RWA,
-- clock for A
CLKA => CLKA,
-- aspect ratio, block, pipeline, write mode configurations for port A
WIDTHA0 => POWER,
WIDTHA1 => POWER,
BLKA => GROUND,
PIPEA => GROUND,
WMODEA => GROUND,
-- inputs concerning port B
-- data in B (1 byte, (7 downto 0))
DINB8 => GROUND,
DINB7 => DINB(7),
DINB6 => DINB(6),
DINB5 => DINB(5),
DINB4 => DINB(4),
DINB3 => DINB(3),
DINB2 => DINB(2),
DINB1 => DINB(1),
DINB0 => DINB(0),
-- address B (512 bytes depth, (8 downto 0))
ADDRB11 => GROUND,
ADDRB10 => GROUND,
ADDRB9 => GROUND,
ADDRB8 => ADDRB(8),
ADDRB7 => ADDRB(7),
ADDRB6 => ADDRB(6),
ADDRB5 => ADDRB(5),
ADDRB4 => ADDRB(4),
ADDRB3 => ADDRB(3),
ADDRB2 => ADDRB(2),
ADDRB1 => ADDRB(1),
ADDRB0 => ADDRB(0),
-- read/ write mode for B
WENB => RWB,
-- clock for B
CLKB => CLKB,
-- aspect ratio, block, pipeline, write mode configurations for port B
WIDTHB0 => POWER,
WIDTHB1 => POWER,
BLKB => GROUND,
PIPEB => GROUND,
WMODEB => GROUND,
-- input reset
RESET => RESETn,
-------------------------------
-- OUTPUTS
-- output concerning port A
-- data out A (1 byte)
DOUTA8 => open,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
DOUTA5 => DOUTA(5),
DOUTA4 => DOUTA(4),
DOUTA3 => DOUTA(3),
DOUTA2 => DOUTA(2),
DOUTA1 => DOUTA(1),
DOUTA0 => DOUTA(0),
-- output concerning port B
-- data out B (1 byte)
DOUTB8 => open,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
DOUTB5 => DOUTB(5),
DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3),
DOUTB2 => DOUTB(2),
DOUTB1 => DOUTB(1),
DOUTB0 => DOUTB(0));
-------------------------------
end RAM4K9;
......
sim/spec/testbench/nanoFIP/wf_dualram_512x8_clka_rd_clkb_wr.vhd → sim/spec/testbench/nanoFIP_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd
View file @ 9aa29601
......@@ -129,7 +129,7 @@ begin
-- end generate;
--------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- for triplication: Combinatorial Majority_Voter
-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
......
sim/spec/testbench/tb_masterFIP.vhd
View file @ 9aa29601
......@@ -21,6 +21,9 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library nanoFIP_lib;
use nanoFIP_lib.all;
entity tb_masterFIP is
end tb_masterFIP;
......
syn/spec/spec_masterfip.xise
View file @ 9aa29601
......@@ -16,11 +16,11 @@
<files>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
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......@@ -28,7 +28,7 @@
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......@@ -40,7 +40,7 @@
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......@@ -60,7 +60,7 @@
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......@@ -76,7 +76,7 @@
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......@@ -92,7 +92,7 @@
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......@@ -100,7 +100,7 @@
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......@@ -112,7 +112,7 @@
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......@@ -120,43 +120,43 @@
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......@@ -180,19 +180,19 @@
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......@@ -232,7 +232,7 @@
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......@@ -300,7 +300,7 @@
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......@@ -308,7 +308,7 @@
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......@@ -328,7 +328,7 @@
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......@@ -344,7 +344,7 @@
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......@@ -480,7 +480,7 @@
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......@@ -628,23 +628,23 @@
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......@@ -652,15 +652,15 @@
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......@@ -670,19 +670,19 @@
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......@@ -694,157 +694,85 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="339"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="340"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="341"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="342"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="343"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="344"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="345"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="346"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="347"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="348"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="349"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="350"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="325"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -1253,8 +1315,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP/dut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spec_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -1277,7 +1339,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spec_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......@@ -1357,7 +1419,10 @@
<binding xil_pn:location="/spec_masterFIP" xil_pn:name="../../top/spec/spec_masterFIP.ucf"/>
</bindings>
<libraries/>
<libraries>
<library xil_pn:name="nanoFIP"/>
<library xil_pn:name="nanoFIP_lib"/>
</libraries>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
......
top/spec/spec_masterfip.vhd
View file @ 9aa29601
......@@ -148,8 +148,6 @@ entity spec_masterfip is
speed_b0_i : in std_logic; -- WorldFIP bus Speed
speed_b1_i : in std_logic;
bus_term_en_n_o : out std_logic; -- WorldFIP bus termination
fd_rxcdn_i : in std_logic; -- FielDrive
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......@@ -430,8 +428,6 @@ begin
-- Bus speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 9aa29601
......@@ -141,34 +141,33 @@ architecture rtl of spec_masterfip_mt is
-- Mock Turtle constants
-- eva: check comments on the WRNC..
-- HMQ out : 6
-- HMQ in : 2
constant c_hmq_config : t_wrn_mqueue_config :=
(out_slot_count => 6,
(out_slot_count => 8,
out_slot_config =>
(0 => (width => 128, entries => 4), -- output of the MT CPU0 with all WorldFIP consumed data
1 => (width => 128, entries => 4), -- output of the MT CPU0 with interrupts
2 => (width => 128, entries => 4), -- output of the MT CPU0 with ack of commands for bus configuration
3 => (width => 128, entries => 4), -- output of the MT CPU1 with ack of commands for bus configuration
4 => (width => 128, entries => 4),
5 => (width => 128, entries => 4),
(0 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP periodic consumed variables
1 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiodic consumed variables
2 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiodic messages
3 => (width => 128, entries => 4), -- output of the MT CPU1 with WorldFIP SMMPS periodic variables
4 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP SMMPS aperiodic variables
5 => (width => 128, entries => 4), -- output of the MT CPU0 with IRQs to the application (variable/messages programmed with an irq flag)
6 => (width => 128, entries => 4), -- output of the MT CPU0 command response
7 => (width => 128, entries => 4), -- output of the MT CPU1 command response
others => (0, 0)),
in_slot_count => 2,
in_slot_config =>
(0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus configuration
1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for...
(0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus configuration (commands like: PROGRAM_BA,HW_RESET, BA_START, BA_RUNNING)
1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for the control of CPU0 (handles commands like: BA_STOP,SET_VAR_PAYLOAD, SET_MSG_PAYLOAD, GET_REPORT, GET_PRESENT_LIST, GET_IDENT_VAR)
-- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report)
others => (0, 0)));
-- eva: do we need the rmq??
-- Remote Message Queue, for playing with White Rabbit/Etherbone
-- 1) outgoing path (CPU -> WR Network): 16 entries x 128 words
-- 2) incoming path (WR Network -> CPU): 16 entries x 128 words.
-- RMQs not used
constant c_rmq_config : t_wrn_mqueue_config :=
(out_slot_count => 1,
out_slot_config =>
(0 => (width => 128, entries => 4),
others => (0, 0)),
in_slot_count => 1,
in_slot_config =>
(0 => (width => 128, entries => 4),
others => (0, 0)));
(out_slot_count => 0,
out_slot_config => (others => (0, 0)),
in_slot_count => 0,
in_slot_config => (others => (0, 0)));
constant c_node_config : t_wr_node_config :=
(app_id => x"0f1dc03e",
......
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