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MasterFIP - Gateware
Commit 6ddb678f authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- removed bus_term_en_n (feature also removed from the board) 

- changes on fmc_masterfip_csr.wb regs
- increased out hmq to 6
- different cpu_mem_sizes between CPU0 and CPU1
- general cleanup
parent 883581d1
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rtl/fmc_masterFIP_core.vhd
View file @ 6ddb678f
......@@ -145,8 +145,6 @@ entity fmc_masterFIP_core is
speed_b0_i : in std_logic; -- 1 Mbps : speed_b1 = 0, speed_b0 = 1
speed_b1_i : in std_logic; -- 2.5 Mbps : speed_b1 = 1, speed_b0 = 0
-- 5 Mbps : speed_b1 = 1, speed_b0 = 1
-- Bus termination
bus_term_en_n_o : out std_logic; -- 150 Ohms termination of the bus -- check again
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
......@@ -228,7 +226,7 @@ architecture rtl of fmc_masterFIP_core is
signal rx_crc_wrong_p, rx_crc_wrong, rx_byte_ready_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_bytes_num : std_logic_vector(8 downto 0); -- up to 263 bytes
signal rx_byte_index, rx_bytes_num : std_logic_vector(15 downto 0);
-- ADC
signal adc_sec_conn_n, adc_prim_conn_n : std_logic;
-- ext_sync
......@@ -302,8 +300,6 @@ begin
mf_ext_sync_tst_n_o => ext_sync_tst_n,
mf_ext_sync_p_cnt_rst_o => ext_sync_p_cnt_host_rst,
mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
-- bus termination
mf_bus_term_en_n_o => bus_term_en_n_o,
-- bus speed
mf_speed_i(1) => speed_b1_i,
mf_speed_i(0) => speed_b0_i,
......@@ -334,9 +330,11 @@ begin
-- rx status
mf_rx_stat_pream_ok_i => rx_fss_received,
mf_rx_stat_frame_ok_i => rx_frame_ok,
mf_rx_stat_frame_err_i => rx_crc_wrong,
mf_rx_stat_frame_err_code_i => "000",
mf_rx_stat_bytes_num_i => rx_bytes_num,
mf_rx_stat_frame_crc_err_i => rx_crc_wrong,
mf_rx_stat_bytes_num_i => rx_bytes_num, -- number of bytes to read from the rx_frame upon rx_frame_ok
-- counting starts after the FSS; includes CTRL, Data, CRC, FES fields
mf_rx_stat_curr_byte_indx_i => rx_byte_index, -- current byte being deserialized
-- counting starts after the FSS; includes CTRL, data, CRC, FES fields
-- rx data
mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg1_i => rx_frame(0),
......@@ -405,6 +403,7 @@ begin
mf_rx_data_reg64_i => rx_frame(63),
mf_rx_data_reg65_i => rx_frame(64),
mf_rx_data_reg66_i => rx_frame(65),
mf_rx_data_reg67_i => rx_frame(66),
-- tx data
mf_tx_data_ctrl_o => tx_ctrl_byte,
mf_tx_data_reg1_o => tx_frame(0),
......@@ -472,11 +471,12 @@ begin
mf_tx_data_reg63_o => tx_frame(62),
mf_tx_data_reg64_o => tx_frame(63),
mf_tx_data_reg65_o => tx_frame(64),
mf_tx_data_reg66_o => tx_frame(65));
mf_tx_data_reg66_o => tx_frame(65),
mf_tx_data_reg67_o => tx_frame(66));
adc_sec_conn_n_o <= '0' when adc_sec_conn_n = '0' else 'Z';
adc_sec_conn_n_o <= '0' when adc_sec_conn_n = '0' else 'Z';
adc_prim_conn_n_o <= '0' when adc_prim_conn_n = '0' else 'Z';
ext_sync_tst_n_o <= '0' when ext_sync_tst_n= '0' else 'Z';
ext_sync_tst_n_o <= '0' when ext_sync_tst_n = '0' else 'Z';
---------------------------------------------------------------------------------------------------
......
rtl/fmc_masterfip_csr.vhd
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rtl/from_nanofip/wf_package.vhd
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rtl/masterFIP_pkg.vhd
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rtl/masterfip_rx.vhd
View file @ 6ddb678f
......@@ -114,17 +114,19 @@ entity masterfip_rx is port(
rx_byte_o : out std_logic_vector(7 downto 0); -- currently retrieved byte
rx_byte_index_o : out std_logic_vector(8 downto 0); -- index of currently retrieved byte
rx_byte_index_o : out std_logic_vector(15 downto 0);-- index of currently retrieved byte
-- counting starts after FSS; it includes the
-- CTRL, DATA, CRC and FES fields
-- CTRL, DATA, CRC and FES fields;
-- normally the value should not exceed 266
rx_ctrl_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_frame_o : out rx_frame_t; -- frame DATA bytes
-- structure with 66 words of 32-bit each
-- this represents the max length of a frame
-- upon the rx_fss_crc_fes_ok_p_o only
-- rx_byte_index_o bytes have to be read by the processor
-- structure with 67 words of 32-bit each = 268 bytes
-- this represents the max length of a frame.
-- Upon the rx_fss_crc_fes_ok_p_o the processor needs
-- to read the rx_ctrl_byte and rx_byte_index_o - 4
-- bytes from the rx_frame_o.
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame with
-- correct FSS, FES & CRC; pulse upon FES detection
......@@ -151,12 +153,12 @@ architecture struc of masterfip_rx is
-- wf_rx_deserializer
signal rx_byte_ready_p, rx_fss_crc_fes_ok_p : std_logic;
signal rx_byte : std_logic_vector (7 downto 0);
-- retreived bytes into 32-bit regs
-- retrieved bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0');
signal word32 : std_logic_vector(31 downto 0);
signal word32_num : integer range 0 to 65;
signal word32_num : integer range 0 to 66;
-- bytes counter
signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0) := (others => '0');
signal rx_byte_index, rx_byte_index_d1 : unsigned(15 downto 0) := (others => '0');
signal bytes_c_rst : std_logic;
......@@ -226,7 +228,11 @@ begin
-- bytes counter --
---------------------------------------------------------------------------------------------------
cmp_rx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 9)
generic map(g_counter_lgth => 16) -- normally max frame size = 268 bytes which would fit in 9 bits;
-- more bits have been added to be able to detect if the
-- serializer is by mistake continuing acquiring bytes;
-- note: the 83ms time-out of the deserializer unit, translates to
-- up to 26000 bytes at the fastest speed 2.5Mbps
port map(
uclk_i => clk_i,
counter_reinit_i => bytes_c_rst,
......
rtl/masterfip_tx.vhd
View file @ 6ddb678f
......@@ -55,7 +55,6 @@
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 30/09/2015 |
-- Version v0.01 |
-- Depends on |
-- |
---------------- |
-- Last changes |
......@@ -138,7 +137,7 @@ architecture struc of masterfip_tx is
signal prod_bytes_c : unsigned(8 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0);
signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 65;
signal word32_num : integer range 0 to 66;
signal word32 : std_logic_vector(31 downto 0);
-- bytes counter
signal bytes_num : std_logic_vector(8 downto 0);
......
rtl/wbgen/fmc_masterfip_csr.htm
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rtl/wbgen/fmc_masterfip_csr.wb
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syn/spec_mt/spec_masterfip_mt.xise
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......@@ -49,7 +49,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......
top/spec/spec_masterfip.vhd
View file @ 6ddb678f
......@@ -57,7 +57,7 @@
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2014 |
-- Date 02/2016 |
-- Version v1 |
-- |
---------------- |
......
top/spec_mt/spec_masterfip_mt.ucf
View file @ 6ddb678f
......@@ -200,10 +200,6 @@ NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
......@@ -258,10 +254,10 @@ NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk;
NET "cmp_mock_turtle/U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback;
NET "cmp_mock_turtle/U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n" TIG;
NET "U_Node_Template/U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
NET "cmp_mock_turtle/U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
top/spec_mt/spec_masterfip_mt.vhd
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