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MasterFIP - Gateware
Commit 86ba9c33 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Update licenses to solderpad2 in all submodules. Rebuilt gateware (still not tested)

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general-cores @ e7c5ad9f
Subproject commit 417e297b228512aa55b0432178ada39e707a2ae5
Subproject commit e7c5ad9f3522b241b30c8a2a691f6823547a2013
gn4124-core @ 3799226c
Subproject commit e3a0bf97e125020c83bff6e40199a717e7fda738
Subproject commit 3799226c5e7bc75489c0a787006963e067ce46bb
mockturtle @ 4de6b6a0
Subproject commit 4bd39aa8778cfbac7e47b779ded5808656289ba3
Subproject commit 4de6b6a0ba4a7c4710a59d242aa1941b68ef0523
urv-core @ 890dfda6
Subproject commit 4d6e4c920923fac8d990b69e17b4a394ca71d0ce
Subproject commit 890dfda6d8a9de5a1cf7e3aa49304d3778745cb0
syn/spec/spec_masterfip_mt_urv.par
View file @ 86ba9c33
Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
pcbexps1:: Thu Jun 07 16:29:34 2018
pcbe13593:: Fri Jun 08 14:20:31 2018
par -w -intstyle ise -ol high -mt off spec_masterfip_mt_urv_map.ncd
spec_masterfip_mt_urv.ncd spec_masterfip_mt_urv.pcf
......@@ -111,8 +111,8 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 12 secs
Finished initial Timing Analysis. REAL time: 12 secs
Starting initial Timing Analysis. REAL time: 11 secs
Finished initial Timing Analysis. REAL time: 11 secs
WARNING:Par:288 - The signal ext_sync_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal fd_wdgn_i_IBUF has no load. PAR will not attempt to route this signal.
......@@ -217,31 +217,31 @@ WARNING:Par:288 - The signal cmp_GN4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_I
Starting Router
Phase 1 : 72751 unrouted; REAL time: 13 secs
Phase 1 : 72751 unrouted; REAL time: 12 secs
Phase 2 : 65734 unrouted; REAL time: 16 secs
Phase 2 : 65734 unrouted; REAL time: 15 secs
Phase 3 : 26849 unrouted; REAL time: 41 secs
Phase 3 : 26849 unrouted; REAL time: 40 secs
Phase 4 : 27985 unrouted; (Setup:349, Hold:8216, Component Switching Limit:0) REAL time: 1 mins 10 secs
Phase 4 : 27985 unrouted; (Setup:349, Hold:8216, Component Switching Limit:0) REAL time: 1 mins 8 secs
Updating file: spec_masterfip_mt_urv.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:675, Hold:7857, Component Switching Limit:0) REAL time: 2 mins 58 secs
Phase 5 : 0 unrouted; (Setup:675, Hold:7857, Component Switching Limit:0) REAL time: 2 mins 54 secs
Phase 6 : 0 unrouted; (Setup:463, Hold:7857, Component Switching Limit:0) REAL time: 3 mins 3 secs
Phase 6 : 0 unrouted; (Setup:463, Hold:7857, Component Switching Limit:0) REAL time: 2 mins 58 secs
Updating file: spec_masterfip_mt_urv.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:0, Hold:7857, Component Switching Limit:0) REAL time: 3 mins 27 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7857, Component Switching Limit:0) REAL time: 3 mins 21 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7857, Component Switching Limit:0) REAL time: 3 mins 27 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7857, Component Switching Limit:0) REAL time: 3 mins 21 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 28 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 22 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 31 secs
Total REAL time to Router completion: 3 mins 31 secs
Total CPU time to Router completion: 3 mins 42 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 25 secs
Total REAL time to Router completion: 3 mins 25 secs
Total CPU time to Router completion: 3 mins 34 secs
Partition Implementation Status
-------------------------------
......@@ -386,10 +386,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 58 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 3 mins 36 secs
Total CPU time to PAR completion: 3 mins 46 secs
Total REAL time to PAR completion: 3 mins 29 secs
Total CPU time to PAR completion: 3 mins 38 secs
Peak Memory Usage: 1050 MB
Peak Memory Usage: 1088 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
syn/spec/spec_masterfip_mt_urv.syr
View file @ 86ba9c33
This diff is collapsed.
syn/spec/spec_masterfip_mt_urv.twr
View file @ 86ba9c33
......@@ -1167,14 +1167,14 @@ Design statistics:
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Thu Jun 7 16:33:37 2018
Analysis completed Fri Jun 8 14:24:26 2018
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 713 MB
Peak Memory Usage: 712 MB
syn/spec/spec_masterfip_mt_urv.xise
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This diff is collapsed.
syn/spec/spec_masterfip_mt_urv_map.mrp
View file @ 86ba9c33
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Jun 7 16:25:16 2018
Mapped Date : Fri Jun 8 14:16:14 2018
Design Summary
--------------
......@@ -103,9 +103,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 5.06
Peak Memory Usage: 1099 MB
Total REAL time to MAP completion: 4 mins 12 secs
Total CPU time to MAP completion: 4 mins 12 secs
Peak Memory Usage: 1135 MB
Total REAL time to MAP completion: 4 mins 10 secs
Total CPU time to MAP completion: 4 mins 10 secs
Table of Contents
-----------------
......
top/spec/spec_masterfip_mt_urv.vhd
View file @ 86ba9c33
......@@ -568,7 +568,6 @@ begin
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => '0',
dma_clk_i => clk_100m_sys,
dma_ack_i => '1',
......@@ -576,7 +575,6 @@ begin
dma_err_i => '0',
dma_rty_i => '0',
dma_dat_i => (others => '0'),
dma_int_i => '0',
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
......@@ -710,4 +708,4 @@ end rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------
\ No newline at end of file
--------------------------------------------------------------------------------------------------
top/spec/spec_reset_gen.vhd
View file @ 86ba9c33
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_reset_gen |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_reset_gen.vhd |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- SOLDERPAD LICENSE |
-- Copyright CERN 2014-2018 |
-- ------------------------------------ |
-- Copyright and related rights are licensed under the Solderpad Hardware License, Version 2.0 |
-- (the "License"); you may not use this file except in compliance with the License. |
-- You may obtain a copy of the License at http://solderpad.org/licenses/SHL-2.0. |
-- Unless required by applicable law or agreed to in writing, software, hardware and materials |
-- distributed under this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR |
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language |
-- governing permissions and limitations under the License. |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
......
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