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MasterFIP - Gateware
Commit 7afaf80f authored by kblantos's avatar kblantos
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Design now supports latest mockturtle, still place&route errors

parent e7bb1c46
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Showing with 465 additions and 23373 deletions
gn4124-core @ 3799226c
Subproject commit c629364388453726da401909b5154306ab4e6930
Subproject commit 3799226c5e7bc75489c0a787006963e067ce46bb
rtl/Manifest.py 0 → 100644
View file @ 7afaf80f
files = [
"decr_counter.vhd",
"fmc_masterFIP_core.vhd",
"incr_counter.vhd",
"masterFIP_pkg.vhd",
"masterfip_rx.vhd",
"masterfip_tx.vhd",
"masterfip_wbgen2_csr.vhd",
"masterfip_wbgen2_pkg.vhd",
"wf_mfp_package.vhd",
]
rtl/fmc_masterFIP_core.vhd
View file @ 7afaf80f
......@@ -155,10 +155,9 @@ use work.masterfip_wbgen2_pkg.all;
use work.masterfip_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
--use work.wrcore_pkg.all;
use work.genram_pkg.all;
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
-- Entity declaration for fmc_masterFIP_core
......@@ -305,7 +304,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE rst: generation of a pulse 1 x WorldFIP-clk-cycles long
cmp_fd_rst_generate: gc_dyn_extend_pulse
cmp_fd_rst_generate: entity work.gc_dyn_extend_pulse
generic map(g_len_width => c_PERIODS_COUNTER_LGTH)
port map
(clk_i => clk_i,
......@@ -321,7 +320,7 @@ begin
---------------------------------------------------------------------------------------------------
-- WBGEN2 REGS FROM/TO MOCK TURTLE --
---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: masterfip_wbgen2_csr
cmp_masterfip_csr: entity work.masterfip_wbgen2_csr
port map
(rst_n_i => rst_n_i,
clk_sys_i => clk_i,
......@@ -346,7 +345,7 @@ begin
ext_sync_term_en_o <= reg_from_mt.ext_sync_ctrl_term_en_o;
-- input synchronizer of the ext_sync_a_i signal
cmp_ext_sync_sync: gc_sync_ffs
cmp_ext_sync_sync: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -355,7 +354,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_ext_sync_deglitch: gc_glitch_filt
cmp_ext_sync_deglitch: entity work.gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
port map -- Note that the filter adds a 100 ns delay to the ext_sync signal
......@@ -366,7 +365,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- rising edge detection on the deglitched signal
cmp_ext_sync_deglitch_p_detect: gc_sync_ffs
cmp_ext_sync_deglitch_p_detect: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -375,7 +374,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter of the number of rising edges
cmp_ext_sync_p_cnt:incr_counter
cmp_ext_sync_p_cnt : entity work.incr_counter
generic map(g_counter_lgth => 32) -- for the fastest macrocycle of 20ms, the counter
-- can keep counting for 2.7 years
port map
......@@ -401,7 +400,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the macrocycle time;
-- the macrocycle length (counter top) should be set once upon the application startup
cmp_macrocycle_time_cnt: decr_counter
cmp_macrocycle_time_cnt : entity work.decr_counter
generic map(width => g_width-1)
port map
(clk_i => clk_i,
......@@ -422,7 +421,7 @@ begin
-- counter counting the number of macrocycles;
-- being a 32-bit counter, for the fastest application of 20 ms macrocycle, the counter can
-- keep counting for 2.7 years; when it fills up it would restart from 0.
cmp_macrocycles_cnt: incr_counter
cmp_macrocycles_cnt: entity work.incr_counter
generic map(g_counter_lgth => g_width)
port map
(clk_i => clk_i,
......@@ -442,7 +441,7 @@ begin
-- and before the transmission of a new frame.
-- turnaround counter
cmp_turnaround_cnt: decr_counter
cmp_turnaround_cnt: entity work.decr_counter
generic map(width => 31)
port map
(clk_i => clk_i,
......@@ -464,7 +463,7 @@ begin
-- (tx_completed_p) or after the reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p) for the
-- case of a RP_DAT_MSG that would be followed by RP_FIN.
cmp_silence_cnt: decr_counter
cmp_silence_cnt: entity work.decr_counter
generic map(width => 31)
port map
(clk_i => clk_i,
......@@ -482,7 +481,7 @@ begin
-- MASTERFIP RX --
---------------------------------------------------------------------------------------------------
-- Note that the deglitching of the fd_rxd_a_i takes place inside the masterfip_rx unit.
cmp_masterfip_rx: masterfip_rx
cmp_masterfip_rx: entity work.masterfip_rx
port map
(clk_i => clk_i,
rst_i => core_rst,
......@@ -560,7 +559,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter of frames with crc errors since the startup or a core reset (not on every macrocycle)
cmp_rx_crc_err_cnt: incr_counter
cmp_rx_crc_err_cnt: entity work.incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
......@@ -573,7 +572,7 @@ begin
-- MASTERFIP TX --
---------------------------------------------------------------------------------------------------
cmp_masterfip_tx: masterfip_tx
cmp_masterfip_tx: entity work.masterfip_tx
port map
(clk_i => clk_i,
rst_i => tx_rst,
......@@ -634,7 +633,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- input synchronizer of the fd_wdgn_a_i signal
cmp_fd_wdgn_sync: gc_sync_ffs
cmp_fd_wdgn_sync: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -645,7 +644,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_fd_wdg_deglitch: gc_glitch_filt
cmp_fd_wdg_deglitch: entity work.gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
......@@ -657,7 +656,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- edge detection
cmp_fd_wdgn_deglitch_p_detect: gc_sync_ffs
cmp_fd_wdgn_deglitch_p_detect: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -687,7 +686,7 @@ begin
-- is inactive.
-- input synchronizer of the fd_rxcdn_a_i signal
cmp_fd_rxcdn_sync: gc_sync_ffs
cmp_fd_rxcdn_sync: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -698,7 +697,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- deglitch filter
cmp_fd_rxcd_deglitch: gc_glitch_filt
cmp_fd_rxcd_deglitch: entity work.gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
......@@ -718,7 +717,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- input synchronizer of the fd_txer_a_i signal
cmp_fd_txer_sync: gc_sync_ffs
cmp_fd_txer_sync: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -727,7 +726,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_fd_txer_deglitch: gc_glitch_filt
cmp_fd_txer_deglitch: entity work.gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
......@@ -739,7 +738,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- edge detection on the fd_txer_filt signal
cmp_fd_txer_deglitch_p_detect: gc_sync_ffs
cmp_fd_txer_deglitch_p_detect: entity work.gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -748,7 +747,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the number of fd_txer_p
cmp_fd_txer_cnt:incr_counter
cmp_fd_txer_cnt : entity work.incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
......@@ -786,7 +785,7 @@ begin
-- Note that a temperature reading is provided every second, with the first one a couple of sec
-- after the board power-up/ reset.
cmp_onewire: gc_ds182x_interface
cmp_onewire: entity work.gc_ds182x_interface
generic map (freq => C_QUARTZ_FREQ_MHZ_INT)
port map
(clk_i => clk_i,
......@@ -799,7 +798,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- pps generator based on the 100 MHz clk
cmp_pps_gen: wf_decr_counter
cmp_pps_gen: entity work.wf_decr_counter
generic map(g_counter_lgth => C_1SEC_CNT_LGTH)
port map
(uclk_i => clk_i,
......
rtl/masterFIP_pkg.vhd
View file @ 7afaf80f
......@@ -14,7 +14,7 @@
-- |
-- Description Definitions of constants, types, entities related to the interface between the |
-- fmc_masterfip_core and the Mock Turtle. |
-- Note that a different package, the wf_package, is used for the WorldFIP specific |
-- Note that a different package, the wf_mfp_package, is used for the WorldFIP specific |
-- constant, types, entities and for the clock constants. |
-- |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
......@@ -43,7 +43,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wf_package.all; -- WorldFIP specifics package
use work.wf_mfp_package.all; -- WorldFIP specifics package
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
......@@ -81,7 +81,7 @@ package masterFIP_pkg is
-- 263.
constant C_MAX_FRAME_WORDS : integer := 67;
constant C_MAX_FRAME_BYTES : integer := 266;
constant C_MFP_MAX_FRAME_BYTES : integer := 266;
constant C_FRAME_WORDS_CNT_LGTH : integer := 7; -- counter overflows after 128 words = 512 bytes
-- for normal rx operation it should not exceed
-- 67 words; for normal tx operation it should
......@@ -105,7 +105,7 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filters --
---------------------------------------------------------------------------------------------------
-- constant C_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
-- constant C_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_mfp_package
---------------------------------------------------------------------------------------------------
......@@ -241,4 +241,4 @@ package masterFIP_pkg is
end masterFIP_pkg;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
rtl/masterfip_rx.vhd
View file @ 7afaf80f
......@@ -97,7 +97,7 @@ use IEEE.math_real.all;
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
......@@ -158,7 +158,7 @@ entity masterfip_rx is port(
rx_fss_received_p_o : out std_logic; -- pulse upon FSS detection (ID/ RP_DAT)
rx_bytes_num_err_o : out std_logic); -- active after the reception of > C_MAX_FRAME_BYTES bytes
rx_bytes_num_err_o : out std_logic); -- active after the reception of > C_MFP_MAX_FRAME_BYTES bytes
-- and until a rst_i OR rst_rx_i
end entity masterfip_rx;
......@@ -200,7 +200,7 @@ begin
-- Deserializer as in the nanoFIP project --
---------------------------------------------------------------------------------------------------
cmp_rx_deglitcher: wf_rx_deglitcher
cmp_rx_deglitcher: entity work.wf_rx_deglitcher
port map(
uclk_i => clk_i,
nfip_rst_i => rx_rst_i,
......@@ -213,7 +213,7 @@ begin
fd_rxd_filt_r_edge_p <= rxd_filt_edge_p and (not fd_rxd_filt_f_edge_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_deserializer: wf_rx_deserializer
cmp_rx_deserializer: entity work.wf_rx_deserializer
port map(
uclk_i => clk_i,
nfip_rst_i => rst_i,
......@@ -238,7 +238,7 @@ begin
rx_fss_crc_fes_ok_p_o <= rx_fss_crc_fes_ok_p;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_osc: wf_rx_osc
cmp_rx_osc: entity work.wf_rx_osc
port map(
uclk_i => clk_i,
rate_i => speed_i,
......@@ -256,7 +256,7 @@ begin
---------------------------------------------------------------------------------------------------
-- bytes counter --
---------------------------------------------------------------------------------------------------
cmp_rx_bytes_cnt: incr_counter
cmp_rx_bytes_cnt: entity work.incr_counter
generic map(g_counter_lgth => C_FRAME_BYTES_CNT_LGTH)
port map(
clk_i => clk_i,
......@@ -271,7 +271,7 @@ begin
---------------------------------------------------------------------------------------------------
-- rx bytes exceeded C_MAX_FRAME_BYTES --
-- rx bytes exceeded C_MFP_MAX_FRAME_BYTES --
---------------------------------------------------------------------------------------------------
-- indication that the rx counter exceeded the max expected number of bytes
p_rx_bytes_num_err: process (clk_i)
......@@ -280,7 +280,7 @@ begin
if rst_i = '1' or rx_rst_i = '1' then
rx_bytes_num_err_o <= '0';
else
if unsigned(rx_byte_index) > C_MAX_FRAME_BYTES then
if unsigned(rx_byte_index) > C_MFP_MAX_FRAME_BYTES then
rx_bytes_num_err_o <= '1';
end if;
end if;
......@@ -393,4 +393,4 @@ end architecture struc;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
rtl/masterfip_tx.vhd
View file @ 7afaf80f
......@@ -96,7 +96,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
......@@ -328,4 +328,4 @@ end architecture struc;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
rtl/masterfip_wbgen2_csr.vhd
View file @ 7afaf80f
......@@ -3,8 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Created : 05/31/18 17:36:43
-- Version : 0x00020100
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -157,7 +157,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
masterfip_ver_id_int <= "00000000000000100000000000000000";
masterfip_ver_id_int <= "00000000000000100000000100000000";
masterfip_rst_core_int <= '0';
masterfip_rst_fd_int <= '0';
masterfip_led_rx_act_int <= '0';
......@@ -2036,3 +2036,4 @@ begin
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
rtl/masterfip_wbgen2_pkg.vhd
View file @ 7afaf80f
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Created : 05/31/18 17:36:43
-- Version : 0x00020100
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -536,538 +533,3 @@ return tmp;
end function;
end package body;
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
<<<<<<< HEAD
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
=======
-- Created : 06/30/17 14:35:27
-- Version : 0x00010000
>>>>>>> cleanup
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package masterfip_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_masterfip_in_registers is record
ds1820_temper_i : std_logic_vector(15 downto 0);
ds1820_id_lsb_i : std_logic_vector(31 downto 0);
ds1820_id_msb_i : std_logic_vector(31 downto 0);
ext_sync_p_cnt_i : std_logic_vector(31 downto 0);
speed_i : std_logic_vector(1 downto 0);
macrocyc_time_cnt_i : std_logic_vector(30 downto 0);
macrocyc_num_cnt_i : std_logic_vector(31 downto 0);
turnar_time_cnt_i : std_logic_vector(30 downto 0);
silen_time_cnt_i : std_logic_vector(30 downto 0);
tx_stat_stop_i : std_logic;
tx_stat_ena_i : std_logic;
tx_stat_curr_byte_indx_i : std_logic_vector(15 downto 0);
fd_wdg_i : std_logic;
fd_cd_i : std_logic;
fd_wdg_tstamp_i : std_logic_vector(31 downto 0);
fd_txer_cnt_i : std_logic_vector(31 downto 0);
fd_txer_tstamp_i : std_logic_vector(31 downto 0);
rx_stat_pream_ok_i : std_logic;
rx_stat_ctrl_byte_ok_i : std_logic;
rx_stat_frame_ok_i : std_logic;
rx_stat_frame_crc_err_i : std_logic;
rx_stat_bytes_num_err_i : std_logic;
rx_stat_bytes_num_i : std_logic_vector(15 downto 0);
rx_stat_curr_word_indx_i : std_logic_vector(7 downto 0);
rx_stat_crc_err_cnt_i : std_logic_vector(31 downto 0);
rx_payld_ctrl_i : std_logic_vector(7 downto 0);
rx_payld_reg1_i : std_logic_vector(31 downto 0);
rx_payld_reg2_i : std_logic_vector(31 downto 0);
rx_payld_reg3_i : std_logic_vector(31 downto 0);
rx_payld_reg4_i : std_logic_vector(31 downto 0);
rx_payld_reg5_i : std_logic_vector(31 downto 0);
rx_payld_reg6_i : std_logic_vector(31 downto 0);
rx_payld_reg7_i : std_logic_vector(31 downto 0);
rx_payld_reg8_i : std_logic_vector(31 downto 0);
rx_payld_reg9_i : std_logic_vector(31 downto 0);
rx_payld_reg10_i : std_logic_vector(31 downto 0);
rx_payld_reg11_i : std_logic_vector(31 downto 0);
rx_payld_reg12_i : std_logic_vector(31 downto 0);
rx_payld_reg13_i : std_logic_vector(31 downto 0);
rx_payld_reg14_i : std_logic_vector(31 downto 0);
rx_payld_reg15_i : std_logic_vector(31 downto 0);
rx_payld_reg16_i : std_logic_vector(31 downto 0);
rx_payld_reg17_i : std_logic_vector(31 downto 0);
rx_payld_reg18_i : std_logic_vector(31 downto 0);
rx_payld_reg19_i : std_logic_vector(31 downto 0);
rx_payld_reg20_i : std_logic_vector(31 downto 0);
rx_payld_reg21_i : std_logic_vector(31 downto 0);
rx_payld_reg22_i : std_logic_vector(31 downto 0);
rx_payld_reg23_i : std_logic_vector(31 downto 0);
rx_payld_reg24_i : std_logic_vector(31 downto 0);
rx_payld_reg25_i : std_logic_vector(31 downto 0);
rx_payld_reg26_i : std_logic_vector(31 downto 0);
rx_payld_reg27_i : std_logic_vector(31 downto 0);
rx_payld_reg28_i : std_logic_vector(31 downto 0);
rx_payld_reg29_i : std_logic_vector(31 downto 0);
rx_payld_reg30_i : std_logic_vector(31 downto 0);
rx_payld_reg31_i : std_logic_vector(31 downto 0);
rx_payld_reg32_i : std_logic_vector(31 downto 0);
rx_payld_reg33_i : std_logic_vector(31 downto 0);
rx_payld_reg34_i : std_logic_vector(31 downto 0);
rx_payld_reg35_i : std_logic_vector(31 downto 0);
rx_payld_reg36_i : std_logic_vector(31 downto 0);
rx_payld_reg37_i : std_logic_vector(31 downto 0);
rx_payld_reg38_i : std_logic_vector(31 downto 0);
rx_payld_reg39_i : std_logic_vector(31 downto 0);
rx_payld_reg40_i : std_logic_vector(31 downto 0);
rx_payld_reg41_i : std_logic_vector(31 downto 0);
rx_payld_reg42_i : std_logic_vector(31 downto 0);
rx_payld_reg43_i : std_logic_vector(31 downto 0);
rx_payld_reg44_i : std_logic_vector(31 downto 0);
rx_payld_reg45_i : std_logic_vector(31 downto 0);
rx_payld_reg46_i : std_logic_vector(31 downto 0);
rx_payld_reg47_i : std_logic_vector(31 downto 0);
rx_payld_reg48_i : std_logic_vector(31 downto 0);
rx_payld_reg49_i : std_logic_vector(31 downto 0);
rx_payld_reg50_i : std_logic_vector(31 downto 0);
rx_payld_reg51_i : std_logic_vector(31 downto 0);
rx_payld_reg52_i : std_logic_vector(31 downto 0);
rx_payld_reg53_i : std_logic_vector(31 downto 0);
rx_payld_reg54_i : std_logic_vector(31 downto 0);
rx_payld_reg55_i : std_logic_vector(31 downto 0);
rx_payld_reg56_i : std_logic_vector(31 downto 0);
rx_payld_reg57_i : std_logic_vector(31 downto 0);
rx_payld_reg58_i : std_logic_vector(31 downto 0);
rx_payld_reg59_i : std_logic_vector(31 downto 0);
rx_payld_reg60_i : std_logic_vector(31 downto 0);
rx_payld_reg61_i : std_logic_vector(31 downto 0);
rx_payld_reg62_i : std_logic_vector(31 downto 0);
rx_payld_reg63_i : std_logic_vector(31 downto 0);
rx_payld_reg64_i : std_logic_vector(31 downto 0);
rx_payld_reg65_i : std_logic_vector(31 downto 0);
rx_payld_reg66_i : std_logic_vector(31 downto 0);
rx_payld_reg67_i : std_logic_vector(31 downto 0);
end record;
constant c_masterfip_in_registers_init_value: t_masterfip_in_registers := (
ds1820_temper_i => (others => '0'),
ds1820_id_lsb_i => (others => '0'),
ds1820_id_msb_i => (others => '0'),
ext_sync_p_cnt_i => (others => '0'),
speed_i => (others => '0'),
macrocyc_time_cnt_i => (others => '0'),
macrocyc_num_cnt_i => (others => '0'),
turnar_time_cnt_i => (others => '0'),
silen_time_cnt_i => (others => '0'),
tx_stat_stop_i => '0',
tx_stat_ena_i => '0',
tx_stat_curr_byte_indx_i => (others => '0'),
fd_wdg_i => '0',
fd_cd_i => '0',
fd_wdg_tstamp_i => (others => '0'),
fd_txer_cnt_i => (others => '0'),
fd_txer_tstamp_i => (others => '0'),
rx_stat_pream_ok_i => '0',
rx_stat_ctrl_byte_ok_i => '0',
rx_stat_frame_ok_i => '0',
rx_stat_frame_crc_err_i => '0',
rx_stat_bytes_num_err_i => '0',
rx_stat_bytes_num_i => (others => '0'),
rx_stat_curr_word_indx_i => (others => '0'),
rx_stat_crc_err_cnt_i => (others => '0'),
rx_payld_ctrl_i => (others => '0'),
rx_payld_reg1_i => (others => '0'),
rx_payld_reg2_i => (others => '0'),
rx_payld_reg3_i => (others => '0'),
rx_payld_reg4_i => (others => '0'),
rx_payld_reg5_i => (others => '0'),
rx_payld_reg6_i => (others => '0'),
rx_payld_reg7_i => (others => '0'),
rx_payld_reg8_i => (others => '0'),
rx_payld_reg9_i => (others => '0'),
rx_payld_reg10_i => (others => '0'),
rx_payld_reg11_i => (others => '0'),
rx_payld_reg12_i => (others => '0'),
rx_payld_reg13_i => (others => '0'),
rx_payld_reg14_i => (others => '0'),
rx_payld_reg15_i => (others => '0'),
rx_payld_reg16_i => (others => '0'),
rx_payld_reg17_i => (others => '0'),
rx_payld_reg18_i => (others => '0'),
rx_payld_reg19_i => (others => '0'),
rx_payld_reg20_i => (others => '0'),
rx_payld_reg21_i => (others => '0'),
rx_payld_reg22_i => (others => '0'),
rx_payld_reg23_i => (others => '0'),
rx_payld_reg24_i => (others => '0'),
rx_payld_reg25_i => (others => '0'),
rx_payld_reg26_i => (others => '0'),
rx_payld_reg27_i => (others => '0'),
rx_payld_reg28_i => (others => '0'),
rx_payld_reg29_i => (others => '0'),
rx_payld_reg30_i => (others => '0'),
rx_payld_reg31_i => (others => '0'),
rx_payld_reg32_i => (others => '0'),
rx_payld_reg33_i => (others => '0'),
rx_payld_reg34_i => (others => '0'),
rx_payld_reg35_i => (others => '0'),
rx_payld_reg36_i => (others => '0'),
rx_payld_reg37_i => (others => '0'),
rx_payld_reg38_i => (others => '0'),
rx_payld_reg39_i => (others => '0'),
rx_payld_reg40_i => (others => '0'),
rx_payld_reg41_i => (others => '0'),
rx_payld_reg42_i => (others => '0'),
rx_payld_reg43_i => (others => '0'),
rx_payld_reg44_i => (others => '0'),
rx_payld_reg45_i => (others => '0'),
rx_payld_reg46_i => (others => '0'),
rx_payld_reg47_i => (others => '0'),
rx_payld_reg48_i => (others => '0'),
rx_payld_reg49_i => (others => '0'),
rx_payld_reg50_i => (others => '0'),
rx_payld_reg51_i => (others => '0'),
rx_payld_reg52_i => (others => '0'),
rx_payld_reg53_i => (others => '0'),
rx_payld_reg54_i => (others => '0'),
rx_payld_reg55_i => (others => '0'),
rx_payld_reg56_i => (others => '0'),
rx_payld_reg57_i => (others => '0'),
rx_payld_reg58_i => (others => '0'),
rx_payld_reg59_i => (others => '0'),
rx_payld_reg60_i => (others => '0'),
rx_payld_reg61_i => (others => '0'),
rx_payld_reg62_i => (others => '0'),
rx_payld_reg63_i => (others => '0'),
rx_payld_reg64_i => (others => '0'),
rx_payld_reg65_i => (others => '0'),
rx_payld_reg66_i => (others => '0'),
rx_payld_reg67_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_masterfip_out_registers is record
ver_id_o : std_logic_vector(31 downto 0);
rst_core_o : std_logic;
rst_fd_o : std_logic;
led_rx_act_o : std_logic;
led_rx_err_o : std_logic;
led_tx_act_o : std_logic;
led_tx_err_o : std_logic;
led_ext_sync_act_o : std_logic;
led_ext_sync_err_o : std_logic;
led_dbg_o : std_logic_vector(23 downto 0);
ext_sync_ctrl_term_en_o : std_logic;
ext_sync_ctrl_dir_o : std_logic;
ext_sync_ctrl_oe_n_o : std_logic;
ext_sync_ctrl_p_cnt_rst_o : std_logic;
ext_sync_ctrl_opt_o : std_logic;
ext_sync_ctrl_safe_wind_o : std_logic;
macrocyc_lgth_o : std_logic_vector(30 downto 0);
macrocyc_start_o : std_logic;
turnar_lgth_o : std_logic_vector(30 downto 0);
turnar_start_o : std_logic;
silen_lgth_o : std_logic_vector(30 downto 0);
silen_start_o : std_logic;
tx_ctrl_rst_o : std_logic;
tx_ctrl_start_o : std_logic;
tx_ctrl_bytes_num_o : std_logic_vector(15 downto 0);
rx_ctrl_rst_o : std_logic;
tx_payld_ctrl_o : std_logic_vector(7 downto 0);
tx_payld_reg1_o : std_logic_vector(31 downto 0);
tx_payld_reg2_o : std_logic_vector(31 downto 0);
tx_payld_reg3_o : std_logic_vector(31 downto 0);
tx_payld_reg4_o : std_logic_vector(31 downto 0);
tx_payld_reg5_o : std_logic_vector(31 downto 0);
tx_payld_reg6_o : std_logic_vector(31 downto 0);
tx_payld_reg7_o : std_logic_vector(31 downto 0);
tx_payld_reg8_o : std_logic_vector(31 downto 0);
tx_payld_reg9_o : std_logic_vector(31 downto 0);
tx_payld_reg10_o : std_logic_vector(31 downto 0);
tx_payld_reg11_o : std_logic_vector(31 downto 0);
tx_payld_reg12_o : std_logic_vector(31 downto 0);
tx_payld_reg13_o : std_logic_vector(31 downto 0);
tx_payld_reg14_o : std_logic_vector(31 downto 0);
tx_payld_reg15_o : std_logic_vector(31 downto 0);
tx_payld_reg16_o : std_logic_vector(31 downto 0);
tx_payld_reg17_o : std_logic_vector(31 downto 0);
tx_payld_reg18_o : std_logic_vector(31 downto 0);
tx_payld_reg19_o : std_logic_vector(31 downto 0);
tx_payld_reg20_o : std_logic_vector(31 downto 0);
tx_payld_reg21_o : std_logic_vector(31 downto 0);
tx_payld_reg22_o : std_logic_vector(31 downto 0);
tx_payld_reg23_o : std_logic_vector(31 downto 0);
tx_payld_reg24_o : std_logic_vector(31 downto 0);
tx_payld_reg25_o : std_logic_vector(31 downto 0);
tx_payld_reg26_o : std_logic_vector(31 downto 0);
tx_payld_reg27_o : std_logic_vector(31 downto 0);
tx_payld_reg28_o : std_logic_vector(31 downto 0);
tx_payld_reg29_o : std_logic_vector(31 downto 0);
tx_payld_reg30_o : std_logic_vector(31 downto 0);
tx_payld_reg31_o : std_logic_vector(31 downto 0);
tx_payld_reg32_o : std_logic_vector(31 downto 0);
tx_payld_reg33_o : std_logic_vector(31 downto 0);
tx_payld_reg34_o : std_logic_vector(31 downto 0);
tx_payld_reg35_o : std_logic_vector(31 downto 0);
tx_payld_reg36_o : std_logic_vector(31 downto 0);
tx_payld_reg37_o : std_logic_vector(31 downto 0);
tx_payld_reg38_o : std_logic_vector(31 downto 0);
tx_payld_reg39_o : std_logic_vector(31 downto 0);
tx_payld_reg40_o : std_logic_vector(31 downto 0);
tx_payld_reg41_o : std_logic_vector(31 downto 0);
tx_payld_reg42_o : std_logic_vector(31 downto 0);
tx_payld_reg43_o : std_logic_vector(31 downto 0);
tx_payld_reg44_o : std_logic_vector(31 downto 0);
tx_payld_reg45_o : std_logic_vector(31 downto 0);
tx_payld_reg46_o : std_logic_vector(31 downto 0);
tx_payld_reg47_o : std_logic_vector(31 downto 0);
tx_payld_reg48_o : std_logic_vector(31 downto 0);
tx_payld_reg49_o : std_logic_vector(31 downto 0);
tx_payld_reg50_o : std_logic_vector(31 downto 0);
tx_payld_reg51_o : std_logic_vector(31 downto 0);
tx_payld_reg52_o : std_logic_vector(31 downto 0);
tx_payld_reg53_o : std_logic_vector(31 downto 0);
tx_payld_reg54_o : std_logic_vector(31 downto 0);
tx_payld_reg55_o : std_logic_vector(31 downto 0);
tx_payld_reg56_o : std_logic_vector(31 downto 0);
tx_payld_reg57_o : std_logic_vector(31 downto 0);
tx_payld_reg58_o : std_logic_vector(31 downto 0);
tx_payld_reg59_o : std_logic_vector(31 downto 0);
tx_payld_reg60_o : std_logic_vector(31 downto 0);
tx_payld_reg61_o : std_logic_vector(31 downto 0);
tx_payld_reg62_o : std_logic_vector(31 downto 0);
tx_payld_reg63_o : std_logic_vector(31 downto 0);
tx_payld_reg64_o : std_logic_vector(31 downto 0);
tx_payld_reg65_o : std_logic_vector(31 downto 0);
tx_payld_reg66_o : std_logic_vector(31 downto 0);
tx_payld_reg67_o : std_logic_vector(31 downto 0);
end record;
constant c_masterfip_out_registers_init_value: t_masterfip_out_registers := (
ver_id_o => (others => '0'),
rst_core_o => '0',
rst_fd_o => '0',
led_rx_act_o => '0',
led_rx_err_o => '0',
led_tx_act_o => '0',
led_tx_err_o => '0',
led_ext_sync_act_o => '0',
led_ext_sync_err_o => '0',
led_dbg_o => (others => '0'),
ext_sync_ctrl_term_en_o => '0',
ext_sync_ctrl_dir_o => '0',
ext_sync_ctrl_oe_n_o => '0',
ext_sync_ctrl_p_cnt_rst_o => '0',
ext_sync_ctrl_opt_o => '0',
ext_sync_ctrl_safe_wind_o => '0',
macrocyc_lgth_o => (others => '0'),
macrocyc_start_o => '0',
turnar_lgth_o => (others => '0'),
turnar_start_o => '0',
silen_lgth_o => (others => '0'),
silen_start_o => '0',
tx_ctrl_rst_o => '0',
tx_ctrl_start_o => '0',
tx_ctrl_bytes_num_o => (others => '0'),
rx_ctrl_rst_o => '0',
tx_payld_ctrl_o => (others => '0'),
tx_payld_reg1_o => (others => '0'),
tx_payld_reg2_o => (others => '0'),
tx_payld_reg3_o => (others => '0'),
tx_payld_reg4_o => (others => '0'),
tx_payld_reg5_o => (others => '0'),
tx_payld_reg6_o => (others => '0'),
tx_payld_reg7_o => (others => '0'),
tx_payld_reg8_o => (others => '0'),
tx_payld_reg9_o => (others => '0'),
tx_payld_reg10_o => (others => '0'),
tx_payld_reg11_o => (others => '0'),
tx_payld_reg12_o => (others => '0'),
tx_payld_reg13_o => (others => '0'),
tx_payld_reg14_o => (others => '0'),
tx_payld_reg15_o => (others => '0'),
tx_payld_reg16_o => (others => '0'),
tx_payld_reg17_o => (others => '0'),
tx_payld_reg18_o => (others => '0'),
tx_payld_reg19_o => (others => '0'),
tx_payld_reg20_o => (others => '0'),
tx_payld_reg21_o => (others => '0'),
tx_payld_reg22_o => (others => '0'),
tx_payld_reg23_o => (others => '0'),
tx_payld_reg24_o => (others => '0'),
tx_payld_reg25_o => (others => '0'),
tx_payld_reg26_o => (others => '0'),
tx_payld_reg27_o => (others => '0'),
tx_payld_reg28_o => (others => '0'),
tx_payld_reg29_o => (others => '0'),
tx_payld_reg30_o => (others => '0'),
tx_payld_reg31_o => (others => '0'),
tx_payld_reg32_o => (others => '0'),
tx_payld_reg33_o => (others => '0'),
tx_payld_reg34_o => (others => '0'),
tx_payld_reg35_o => (others => '0'),
tx_payld_reg36_o => (others => '0'),
tx_payld_reg37_o => (others => '0'),
tx_payld_reg38_o => (others => '0'),
tx_payld_reg39_o => (others => '0'),
tx_payld_reg40_o => (others => '0'),
tx_payld_reg41_o => (others => '0'),
tx_payld_reg42_o => (others => '0'),
tx_payld_reg43_o => (others => '0'),
tx_payld_reg44_o => (others => '0'),
tx_payld_reg45_o => (others => '0'),
tx_payld_reg46_o => (others => '0'),
tx_payld_reg47_o => (others => '0'),
tx_payld_reg48_o => (others => '0'),
tx_payld_reg49_o => (others => '0'),
tx_payld_reg50_o => (others => '0'),
tx_payld_reg51_o => (others => '0'),
tx_payld_reg52_o => (others => '0'),
tx_payld_reg53_o => (others => '0'),
tx_payld_reg54_o => (others => '0'),
tx_payld_reg55_o => (others => '0'),
tx_payld_reg56_o => (others => '0'),
tx_payld_reg57_o => (others => '0'),
tx_payld_reg58_o => (others => '0'),
tx_payld_reg59_o => (others => '0'),
tx_payld_reg60_o => (others => '0'),
tx_payld_reg61_o => (others => '0'),
tx_payld_reg62_o => (others => '0'),
tx_payld_reg63_o => (others => '0'),
tx_payld_reg64_o => (others => '0'),
tx_payld_reg65_o => (others => '0'),
tx_payld_reg66_o => (others => '0'),
tx_payld_reg67_o => (others => '0')
);
function "or" (left, right: t_masterfip_in_registers) return t_masterfip_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body masterfip_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_masterfip_in_registers) return t_masterfip_in_registers is
variable tmp: t_masterfip_in_registers;
begin
tmp.ds1820_temper_i := f_x_to_zero(left.ds1820_temper_i) or f_x_to_zero(right.ds1820_temper_i);
tmp.ds1820_id_lsb_i := f_x_to_zero(left.ds1820_id_lsb_i) or f_x_to_zero(right.ds1820_id_lsb_i);
tmp.ds1820_id_msb_i := f_x_to_zero(left.ds1820_id_msb_i) or f_x_to_zero(right.ds1820_id_msb_i);
tmp.ext_sync_p_cnt_i := f_x_to_zero(left.ext_sync_p_cnt_i) or f_x_to_zero(right.ext_sync_p_cnt_i);
tmp.speed_i := f_x_to_zero(left.speed_i) or f_x_to_zero(right.speed_i);
tmp.macrocyc_time_cnt_i := f_x_to_zero(left.macrocyc_time_cnt_i) or f_x_to_zero(right.macrocyc_time_cnt_i);
tmp.macrocyc_num_cnt_i := f_x_to_zero(left.macrocyc_num_cnt_i) or f_x_to_zero(right.macrocyc_num_cnt_i);
tmp.turnar_time_cnt_i := f_x_to_zero(left.turnar_time_cnt_i) or f_x_to_zero(right.turnar_time_cnt_i);
tmp.silen_time_cnt_i := f_x_to_zero(left.silen_time_cnt_i) or f_x_to_zero(right.silen_time_cnt_i);
tmp.tx_stat_stop_i := f_x_to_zero(left.tx_stat_stop_i) or f_x_to_zero(right.tx_stat_stop_i);
tmp.tx_stat_ena_i := f_x_to_zero(left.tx_stat_ena_i) or f_x_to_zero(right.tx_stat_ena_i);
tmp.tx_stat_curr_byte_indx_i := f_x_to_zero(left.tx_stat_curr_byte_indx_i) or f_x_to_zero(right.tx_stat_curr_byte_indx_i);
tmp.fd_wdg_i := f_x_to_zero(left.fd_wdg_i) or f_x_to_zero(right.fd_wdg_i);
tmp.fd_cd_i := f_x_to_zero(left.fd_cd_i) or f_x_to_zero(right.fd_cd_i);
tmp.fd_wdg_tstamp_i := f_x_to_zero(left.fd_wdg_tstamp_i) or f_x_to_zero(right.fd_wdg_tstamp_i);
tmp.fd_txer_cnt_i := f_x_to_zero(left.fd_txer_cnt_i) or f_x_to_zero(right.fd_txer_cnt_i);
tmp.fd_txer_tstamp_i := f_x_to_zero(left.fd_txer_tstamp_i) or f_x_to_zero(right.fd_txer_tstamp_i);
tmp.rx_stat_pream_ok_i := f_x_to_zero(left.rx_stat_pream_ok_i) or f_x_to_zero(right.rx_stat_pream_ok_i);
tmp.rx_stat_ctrl_byte_ok_i := f_x_to_zero(left.rx_stat_ctrl_byte_ok_i) or f_x_to_zero(right.rx_stat_ctrl_byte_ok_i);
tmp.rx_stat_frame_ok_i := f_x_to_zero(left.rx_stat_frame_ok_i) or f_x_to_zero(right.rx_stat_frame_ok_i);
tmp.rx_stat_frame_crc_err_i := f_x_to_zero(left.rx_stat_frame_crc_err_i) or f_x_to_zero(right.rx_stat_frame_crc_err_i);
tmp.rx_stat_bytes_num_err_i := f_x_to_zero(left.rx_stat_bytes_num_err_i) or f_x_to_zero(right.rx_stat_bytes_num_err_i);
tmp.rx_stat_bytes_num_i := f_x_to_zero(left.rx_stat_bytes_num_i) or f_x_to_zero(right.rx_stat_bytes_num_i);
tmp.rx_stat_curr_word_indx_i := f_x_to_zero(left.rx_stat_curr_word_indx_i) or f_x_to_zero(right.rx_stat_curr_word_indx_i);
tmp.rx_stat_crc_err_cnt_i := f_x_to_zero(left.rx_stat_crc_err_cnt_i) or f_x_to_zero(right.rx_stat_crc_err_cnt_i);
tmp.rx_payld_ctrl_i := f_x_to_zero(left.rx_payld_ctrl_i) or f_x_to_zero(right.rx_payld_ctrl_i);
tmp.rx_payld_reg1_i := f_x_to_zero(left.rx_payld_reg1_i) or f_x_to_zero(right.rx_payld_reg1_i);
tmp.rx_payld_reg2_i := f_x_to_zero(left.rx_payld_reg2_i) or f_x_to_zero(right.rx_payld_reg2_i);
tmp.rx_payld_reg3_i := f_x_to_zero(left.rx_payld_reg3_i) or f_x_to_zero(right.rx_payld_reg3_i);
tmp.rx_payld_reg4_i := f_x_to_zero(left.rx_payld_reg4_i) or f_x_to_zero(right.rx_payld_reg4_i);
tmp.rx_payld_reg5_i := f_x_to_zero(left.rx_payld_reg5_i) or f_x_to_zero(right.rx_payld_reg5_i);
tmp.rx_payld_reg6_i := f_x_to_zero(left.rx_payld_reg6_i) or f_x_to_zero(right.rx_payld_reg6_i);
tmp.rx_payld_reg7_i := f_x_to_zero(left.rx_payld_reg7_i) or f_x_to_zero(right.rx_payld_reg7_i);
tmp.rx_payld_reg8_i := f_x_to_zero(left.rx_payld_reg8_i) or f_x_to_zero(right.rx_payld_reg8_i);
tmp.rx_payld_reg9_i := f_x_to_zero(left.rx_payld_reg9_i) or f_x_to_zero(right.rx_payld_reg9_i);
tmp.rx_payld_reg10_i := f_x_to_zero(left.rx_payld_reg10_i) or f_x_to_zero(right.rx_payld_reg10_i);
tmp.rx_payld_reg11_i := f_x_to_zero(left.rx_payld_reg11_i) or f_x_to_zero(right.rx_payld_reg11_i);
tmp.rx_payld_reg12_i := f_x_to_zero(left.rx_payld_reg12_i) or f_x_to_zero(right.rx_payld_reg12_i);
tmp.rx_payld_reg13_i := f_x_to_zero(left.rx_payld_reg13_i) or f_x_to_zero(right.rx_payld_reg13_i);
tmp.rx_payld_reg14_i := f_x_to_zero(left.rx_payld_reg14_i) or f_x_to_zero(right.rx_payld_reg14_i);
tmp.rx_payld_reg15_i := f_x_to_zero(left.rx_payld_reg15_i) or f_x_to_zero(right.rx_payld_reg15_i);
tmp.rx_payld_reg16_i := f_x_to_zero(left.rx_payld_reg16_i) or f_x_to_zero(right.rx_payld_reg16_i);
tmp.rx_payld_reg17_i := f_x_to_zero(left.rx_payld_reg17_i) or f_x_to_zero(right.rx_payld_reg17_i);
tmp.rx_payld_reg18_i := f_x_to_zero(left.rx_payld_reg18_i) or f_x_to_zero(right.rx_payld_reg18_i);
tmp.rx_payld_reg19_i := f_x_to_zero(left.rx_payld_reg19_i) or f_x_to_zero(right.rx_payld_reg19_i);
tmp.rx_payld_reg20_i := f_x_to_zero(left.rx_payld_reg20_i) or f_x_to_zero(right.rx_payld_reg20_i);
tmp.rx_payld_reg21_i := f_x_to_zero(left.rx_payld_reg21_i) or f_x_to_zero(right.rx_payld_reg21_i);
tmp.rx_payld_reg22_i := f_x_to_zero(left.rx_payld_reg22_i) or f_x_to_zero(right.rx_payld_reg22_i);
tmp.rx_payld_reg23_i := f_x_to_zero(left.rx_payld_reg23_i) or f_x_to_zero(right.rx_payld_reg23_i);
tmp.rx_payld_reg24_i := f_x_to_zero(left.rx_payld_reg24_i) or f_x_to_zero(right.rx_payld_reg24_i);
tmp.rx_payld_reg25_i := f_x_to_zero(left.rx_payld_reg25_i) or f_x_to_zero(right.rx_payld_reg25_i);
tmp.rx_payld_reg26_i := f_x_to_zero(left.rx_payld_reg26_i) or f_x_to_zero(right.rx_payld_reg26_i);
tmp.rx_payld_reg27_i := f_x_to_zero(left.rx_payld_reg27_i) or f_x_to_zero(right.rx_payld_reg27_i);
tmp.rx_payld_reg28_i := f_x_to_zero(left.rx_payld_reg28_i) or f_x_to_zero(right.rx_payld_reg28_i);
tmp.rx_payld_reg29_i := f_x_to_zero(left.rx_payld_reg29_i) or f_x_to_zero(right.rx_payld_reg29_i);
tmp.rx_payld_reg30_i := f_x_to_zero(left.rx_payld_reg30_i) or f_x_to_zero(right.rx_payld_reg30_i);
tmp.rx_payld_reg31_i := f_x_to_zero(left.rx_payld_reg31_i) or f_x_to_zero(right.rx_payld_reg31_i);
tmp.rx_payld_reg32_i := f_x_to_zero(left.rx_payld_reg32_i) or f_x_to_zero(right.rx_payld_reg32_i);
tmp.rx_payld_reg33_i := f_x_to_zero(left.rx_payld_reg33_i) or f_x_to_zero(right.rx_payld_reg33_i);
tmp.rx_payld_reg34_i := f_x_to_zero(left.rx_payld_reg34_i) or f_x_to_zero(right.rx_payld_reg34_i);
tmp.rx_payld_reg35_i := f_x_to_zero(left.rx_payld_reg35_i) or f_x_to_zero(right.rx_payld_reg35_i);
tmp.rx_payld_reg36_i := f_x_to_zero(left.rx_payld_reg36_i) or f_x_to_zero(right.rx_payld_reg36_i);
tmp.rx_payld_reg37_i := f_x_to_zero(left.rx_payld_reg37_i) or f_x_to_zero(right.rx_payld_reg37_i);
tmp.rx_payld_reg38_i := f_x_to_zero(left.rx_payld_reg38_i) or f_x_to_zero(right.rx_payld_reg38_i);
tmp.rx_payld_reg39_i := f_x_to_zero(left.rx_payld_reg39_i) or f_x_to_zero(right.rx_payld_reg39_i);
tmp.rx_payld_reg40_i := f_x_to_zero(left.rx_payld_reg40_i) or f_x_to_zero(right.rx_payld_reg40_i);
tmp.rx_payld_reg41_i := f_x_to_zero(left.rx_payld_reg41_i) or f_x_to_zero(right.rx_payld_reg41_i);
tmp.rx_payld_reg42_i := f_x_to_zero(left.rx_payld_reg42_i) or f_x_to_zero(right.rx_payld_reg42_i);
tmp.rx_payld_reg43_i := f_x_to_zero(left.rx_payld_reg43_i) or f_x_to_zero(right.rx_payld_reg43_i);
tmp.rx_payld_reg44_i := f_x_to_zero(left.rx_payld_reg44_i) or f_x_to_zero(right.rx_payld_reg44_i);
tmp.rx_payld_reg45_i := f_x_to_zero(left.rx_payld_reg45_i) or f_x_to_zero(right.rx_payld_reg45_i);
tmp.rx_payld_reg46_i := f_x_to_zero(left.rx_payld_reg46_i) or f_x_to_zero(right.rx_payld_reg46_i);
tmp.rx_payld_reg47_i := f_x_to_zero(left.rx_payld_reg47_i) or f_x_to_zero(right.rx_payld_reg47_i);
tmp.rx_payld_reg48_i := f_x_to_zero(left.rx_payld_reg48_i) or f_x_to_zero(right.rx_payld_reg48_i);
tmp.rx_payld_reg49_i := f_x_to_zero(left.rx_payld_reg49_i) or f_x_to_zero(right.rx_payld_reg49_i);
tmp.rx_payld_reg50_i := f_x_to_zero(left.rx_payld_reg50_i) or f_x_to_zero(right.rx_payld_reg50_i);
tmp.rx_payld_reg51_i := f_x_to_zero(left.rx_payld_reg51_i) or f_x_to_zero(right.rx_payld_reg51_i);
tmp.rx_payld_reg52_i := f_x_to_zero(left.rx_payld_reg52_i) or f_x_to_zero(right.rx_payld_reg52_i);
tmp.rx_payld_reg53_i := f_x_to_zero(left.rx_payld_reg53_i) or f_x_to_zero(right.rx_payld_reg53_i);
tmp.rx_payld_reg54_i := f_x_to_zero(left.rx_payld_reg54_i) or f_x_to_zero(right.rx_payld_reg54_i);
tmp.rx_payld_reg55_i := f_x_to_zero(left.rx_payld_reg55_i) or f_x_to_zero(right.rx_payld_reg55_i);
tmp.rx_payld_reg56_i := f_x_to_zero(left.rx_payld_reg56_i) or f_x_to_zero(right.rx_payld_reg56_i);
tmp.rx_payld_reg57_i := f_x_to_zero(left.rx_payld_reg57_i) or f_x_to_zero(right.rx_payld_reg57_i);
tmp.rx_payld_reg58_i := f_x_to_zero(left.rx_payld_reg58_i) or f_x_to_zero(right.rx_payld_reg58_i);
tmp.rx_payld_reg59_i := f_x_to_zero(left.rx_payld_reg59_i) or f_x_to_zero(right.rx_payld_reg59_i);
tmp.rx_payld_reg60_i := f_x_to_zero(left.rx_payld_reg60_i) or f_x_to_zero(right.rx_payld_reg60_i);
tmp.rx_payld_reg61_i := f_x_to_zero(left.rx_payld_reg61_i) or f_x_to_zero(right.rx_payld_reg61_i);
tmp.rx_payld_reg62_i := f_x_to_zero(left.rx_payld_reg62_i) or f_x_to_zero(right.rx_payld_reg62_i);
tmp.rx_payld_reg63_i := f_x_to_zero(left.rx_payld_reg63_i) or f_x_to_zero(right.rx_payld_reg63_i);
tmp.rx_payld_reg64_i := f_x_to_zero(left.rx_payld_reg64_i) or f_x_to_zero(right.rx_payld_reg64_i);
tmp.rx_payld_reg65_i := f_x_to_zero(left.rx_payld_reg65_i) or f_x_to_zero(right.rx_payld_reg65_i);
tmp.rx_payld_reg66_i := f_x_to_zero(left.rx_payld_reg66_i) or f_x_to_zero(right.rx_payld_reg66_i);
tmp.rx_payld_reg67_i := f_x_to_zero(left.rx_payld_reg67_i) or f_x_to_zero(right.rx_payld_reg67_i);
return tmp;
end function;
end package body;
rtl/wf_package.vhd → rtl/wf_mfp_package.vhd
View file @ 7afaf80f
......@@ -7,16 +7,16 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_PACKAGE |
-- wf_mfp_package |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_package.vhd |
-- File wf_mfp_package.vhd |
-- |
-- Description Definitions of constants, types, entities, functions related to WorldFIP |
-- serialization and deserialization; the package is essential for all the modules |
-- coming from the nanoFIP design. |
-- As in the masterFIP design the clk is 100 MHz and in the nanoFIP 40 MHz it was |
-- necessary to have a new wf_package. In principle the nanoFIP design could have |
-- necessary to have a new wf_mfp_package. In principle the nanoFIP design could have |
-- been modified to accept generics rather than constants, however as it is a stable |
-- design it was decided to keep it as it is and use for synthesis this package |
-- rather than the one coming with the nanoFIP submodule. |
......@@ -53,9 +53,9 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Package declaration for wf_package
-- Package declaration for wf_mfp_package
--=================================================================================================
package wf_package is
package wf_mfp_package is
---------------------------------------------------------------------------------------------------
......@@ -387,13 +387,13 @@ end component wf_rx_osc;
end wf_package;
end wf_mfp_package;
--=================================================================================================
-- package body
--=================================================================================================
package body wf_package is
package body wf_mfp_package is
---------------------------------------------------------------------------------------------------
......@@ -420,10 +420,10 @@ package body wf_package is
end wf_package;
end wf_mfp_package;
--=================================================================================================
-- package end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
syn/spec/Manifest.py 0 → 100644
View file @ 7afaf80f
action = "synthesis"
target = "xilinx"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
#syn_top = "spec_masterfip_mt_urv"
#syn_project = "spec_masterfip_mt_urv.xise"
#top_module = "spec_masterfip_mt_urv"
syn_top = "spec_masterfip_mt"
syn_project = "spec_masterfip_mt.xise"
syn_module = "spec_masterfip_mt"
syn_tool = "ise"
modules = {
"local" : [
"../../top/spec",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"ssh://git@gitlab.cern.ch:7999/coht/mockturtle.git",
"git://ohwr.org/cern-fip/nanofip/nanofip-gateware.git",
],
}
syn/spec/spec_masterfip_mt.par deleted 100644 → 0
View file @ e7bb1c46
Release 14.7 par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Thu Jan 17 18:18:19 2019
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
Constraints file: spec_masterfip_mt.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"spec_masterfip_mt" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 12,668 out of 54,576 23%
Number used as Flip Flops: 12,666
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 2
Number of Slice LUTs: 15,734 out of 27,288 57%
Number used as logic: 12,556 out of 27,288 46%
Number using O6 output only: 10,426
Number using O5 output only: 466
Number using O5 and O6: 1,664
Number used as ROM: 0
Number used as Memory: 2,680 out of 6,408 41%
Number used as Dual Port RAM: 2,680
Number using O6 output only: 2,560
Number using O5 output only: 0
Number using O5 and O6: 120
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Number used exclusively as route-thrus: 498
Number with same-slice register load: 470
Number with same-slice carry load: 28
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 5,569 out of 6,822 81%
Number of MUXCYs used: 1,520 out of 13,644 11%
Number of LUT Flip Flop pairs used: 19,297
Number with an unused Flip Flop: 7,659 out of 19,297 39%
Number with an unused LUT: 3,563 out of 19,297 18%
Number of fully used LUT-FF pairs: 8,075 out of 19,297 41%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 94 out of 296 31%
Number of LOCed IOBs: 94 out of 94 100%
IOB Flip Flops: 10
Specific Feature Utilization:
Number of RAMB16BWERs: 85 out of 116 73%
Number of RAMB8BWERs: 25 out of 232 10%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 29 out of 376 7%
Number used as ILOGIC2s: 9
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 21 out of 376 5%
Number used as OLOGIC2s: 1
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 6 out of 58 10%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 2 out of 4 50%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p_wr_req_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal p_wr_req_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tx_error_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 110289 unrouted; REAL time: 20 secs
Phase 2 : 101662 unrouted; REAL time: 23 secs
Phase 3 : 51539 unrouted; REAL time: 1 mins 12 secs
Phase 4 : 53338 unrouted; (Setup:0, Hold:3107, Component Switching Limit:0) REAL time: 1 mins 29 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 41 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 47 secs
Total REAL time to Router completion: 8 mins 47 secs
Total CPU time to Router completion: 8 mins 55 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/clk_ | | | | | |
| sys | BUFGMUX_X2Y3| No | 4507 | 0.549 | 1.760 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 191 | 0.493 | 1.704 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/io_clk | Local| | 41 | 0.064 | 1.562 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 7
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.030ns| 9.970ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.293ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.056ns| 4.944ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.051ns| | 0| 0
PERIOD TIMEGRP "cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
rx_pllout_x1" TS_cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
buf_P_clk PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
24_Core_cmp_clk_in_buf_P_clk = PERIOD | | | | |
TIMEGRP "cmp_mock_turtle_gen | | | | |
_with_gennum_U_GN4124_Core_cmp_clk_in_buf | | | | |
_P_clk" TS_U_Node_Template_U_GN41 | | | | |
24_Core_cmp_clk_in_P_clk HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_U_Node_Template_U_GN4124_Core_cmp_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
in_P_clk = PERIOD TIMEGRP "U_Node | | | | |
_Template/gen_with_gennum.U_GN4124_Core/c | | | | |
mp_clk_in/P_clk" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | MINLOWPULSE | 4.666ns| 3.334ns| 0| 0
clk_125m_pllref_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | MINLOWPULSE | 4.666ns| 3.334ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys = PERIO | MINPERIOD | 6.876ns| 3.124ns| 0| 0
D TIMEGRP "cmp_mock_turtle_pllout | | | | |
_clk_sys" TS_clk_125m_pllref_p_i / 0.8 HI | | | | |
GH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | N/A | N/A| N/A| N/A| N/A
24_Core_cmp_clk_in_feedback = PERIOD | | | | |
TIMEGRP "cmp_mock_turtle/gen_ | | | | |
with_gennum.U_GN4124_Core/cmp_clk_in/feed | | | | |
back" 20 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | N/A | N/A| N/A| N/A| N/A
24_Core_cmp_clk_in_rx_pllout_xs_int = | | | | |
PERIOD TIMEGRP "cmp_mock_tur | | | | |
tle_gen_with_gennum_U_GN4124_Core_cmp_clk | | | | |
_in_rx_pllout_xs_int" TS_cmp_mock | | | | |
_turtle_gen_with_gennum_U_GN4124_Core_cmp | | | | |
_clk_in_buf_P_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_clk_125m_pllref_p_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_p_i | 8.000ns| 3.334ns| 2.499ns| 0| 0| 0| 0|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 3.124ns| N/A| 0| 0| 0| 0|
| sys | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_clk_125m_pllref_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.976ns| 0| 0| 0| 4838562|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.970ns| N/A| 0| 0| 4838562| 0|
| sys_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.944ns| 0| 0| 0| 3371|
|e_cmp_clk_in_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.944ns| 0| 0| 0| 3371|
| nnum_U_GN4124_Core_cmp_clk_in_| | | | | | | |
| buf_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_xs_int | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.944ns| N/A| 0| 0| 3371| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 8 mins 55 secs
Total CPU time to PAR completion: 9 mins 3 secs
Peak Memory Usage: 666 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 31
Number of info messages: 1
Writing design to file spec_masterfip_mt.ncd
PAR done!
syn/spec/spec_masterfip_mt.syr deleted 100644 → 0
View file @ e7bb1c46
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syn/spec/spec_masterfip_mt.twr deleted 100644 → 0
View file @ e7bb1c46
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syn/spec/spec_masterfip_mt.xise deleted 100644 → 0
View file @ e7bb1c46
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syn/spec/spec_masterfip_mt_map.mrp deleted 100644 → 0
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top/spec/Manifest.py 0 → 100644
View file @ 7afaf80f
files = [
"spec_masterfip_mt.ucf",
# "spec_masterfip_mt_urv.vhd",
"spec_masterfip_mt.vhd",
"spec_reset_gen.vhd",
]
modules = {
"local" : [
"../../rtl",
],
}
top/spec/spec_masterfip_mt.ucf
View file @ 7afaf80f
......@@ -154,20 +154,6 @@ NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0 P2V5: SPEC DAC
#----------------------------------------
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
NET "dac_cs_n_o[1]" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
......@@ -265,13 +251,18 @@ NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
#NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
NET "cmp_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
#NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
NET "cmp_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
#NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
NET "cmp_GN4124_Core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/06/30
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
#NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
NET "cmp_GN4124_Core/cmp_clk_in/feedback" TNM_NET = cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_mock_turtle_gen_with_gennum_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" 20 ns HIGH 50%;
top/spec/spec_masterfip_mt.vhd → top/spec/spec_masterfip_mt_urv.vhd
View file @ 7afaf80f
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- spec_masterfip_mt |
-- spec_masterfip_mt_urv |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_masterfip_mt.vhd |
-- File spec_masterfip_mt_urv.vhd |
-- |
-- Description Top level of the masterFIP design with Mock Turtle on a SPEC carrier. |
-- |
......@@ -45,7 +45,7 @@
-- | | |___| | | |
-- | |_________________________________________| | |
-- |______________________________________________________________________| |
-- Figure 1: spec_masterfip_mt architecture |
-- Figure 1: spec_masterfip_mt_urv architecture |
-- |
-- |
-- FMC MASTERFIP CORE: |
......@@ -147,17 +147,19 @@ use IEEE.numeric_std.all; -- conversion functions
library work;
use work.wishbone_pkg.all; -- for the wb_crossbar
use work.spec_node_pkg.all; -- for the spec_node_template definition
use work.wr_node_pkg.all; -- for the spec_node_template configuration
use work.wrn_mqueue_pkg.all; -- for the HMQ
use work.gn4124_core_pkg.all; -- for the gennum 4124 core
use work.mt_mqueue_pkg.all; -- for the HMQ
use work.mock_turtle_pkg.all; -- for the Mockturtle
use work.masterFIP_pkg.all; -- for the fmc_masterfip_core definition
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
library unisim;
use unisim.vcomponents.all;
entity spec_masterfip_mt is
entity spec_masterfip_mt_urv is
generic (g_simul : boolean := false);
port
(-- Carrier signals
( -- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference,
......@@ -191,11 +193,6 @@ entity spec_masterfip_mt is
tx_error_i : in std_logic; -- transmit error
vc_rdy_i : in std_logic_vector(1 downto 0); -- channel ready
-- DAC I2C (driven by MT to the VCXO mid range -fixed value- for max stability on the 100 MHz clk)
dac_cs_n_o : out std_logic_vector(1 downto 0); -- 0: select SPEC 25MHz OSC5 VCXO
dac_sclk_o : out std_logic; -- 1: select SPEC 20MHz OSC1 VCXO
dac_din_o : out std_logic;
-- SPEC LEDs
led_green_o : out std_logic; -- blinking with clk_100m_sys
led_red_o : out std_logic; -- active during a PCIe rst, l_rst_n_i
......@@ -246,13 +243,13 @@ entity spec_masterfip_mt is
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic);
end spec_masterfip_mt;
end spec_masterfip_mt_urv;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip_mt is
architecture rtl of spec_masterfip_mt_urv is
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CONSTANTS --
......@@ -283,48 +280,59 @@ architecture rtl of spec_masterfip_mt is
-- as well as requests for report data, requests for the scheduling of aperiodic traffic
-- (presence/ identification) etc (CPU1 again passes these requests into the Shared Memory).
constant C_HMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 8, -- MT -> towards the host
out_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
2 => (width => 128, entries => 4),
3 => (width => 128, entries => 4),
4 => (width => 128, entries => 4),
5 => (width => 128, entries => 4),
6 => (width => 128, entries => 4),
7 => (width => 128, entries => 4),
others => (0, 0)),
in_slot_count => 2, -- host -> towards MT
in_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
others => (0, 0)));
constant C_NODE_CONFIG : t_mt_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_config => (0 => (memsize => 24576, -- in words; the size should be enough for the storage of the RT sw running on CPU0 and for the macrocycle configuration
hmq_config => (7, (others => (2, 7, 2, x"0000_0000",true))), -- 4 entries, 128 wide, 2 header bits
rmq_config => (0, (others => (c_DUMMY_MT_MQUEUE_SLOT)))),
1 => (memsize => 2048,
hmq_config => (2, (others => (2, 7, 2, x"0000_0000",true))),
rmq_config => (0, (others => (c_DUMMY_MT_MQUEUE_SLOT)))),
others => (0, c_MT_DEFAULT_MQUEUE_CONFIG, c_MT_DEFAULT_MQUEUE_CONFIG)),
shared_mem_size => 8192); -- 65536 in bytes = 16384 words
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RMQs not used!
constant C_RMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 0,
out_slot_config => (others => (0, 0)),
in_slot_count => 0,
in_slot_config => (others => (0, 0)));
-- masterFIP crossbar constants
constant C_SLAVE_ADDR : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
constant C_SLAVE_MASK : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant C_NODE_CONFIG : t_wr_node_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (98304, 8192, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
-- for the storage of the RT sw running on CPU0
-- and for the macrocycle configuration
hmq_config => C_HMQ_CONFIG,
rmq_config => C_RMQ_CONFIG,
shared_mem_size => 65536); -- in bytes
-- mockturtle interconnect crossbar constants
constant c_NUM_WB_MASTERS : integer := 3;
constant c_NUM_WB_SLAVES : integer := 1; --gn4124 port
constant c_MASTER_GENNUM : integer := 0;
constant c_SLAVE_FMC0 : integer := 0;
constant c_SLAVE_WR_NODE : integer := 1;
constant c_SLAVE_VIC : integer := 2;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS - 1 downto 0) :=
(
c_SLAVE_FMC0 => f_sdb_embed_device(cc_dummy_sdb_device, x"00010000"),
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00002000"),
c_SLAVE_WR_NODE => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000")
);
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant C_SLAVE_ADDR : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
constant C_SLAVE_MASK : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 2) :=
(0 => x"00000000",
1 => x"00020000", -- WRNC Mqueue interrupt
2 => x"00020001" -- WRNC Debug Msg interrupt
);
---------------------------------------------------------------------------------------------------
......@@ -332,12 +340,20 @@ architecture rtl of spec_masterfip_mt is
---------------------------------------------------------------------------------------------------
-- clk, reset
signal clk_100m_sys : std_logic;
signal clk_125m_pllref : std_logic;
signal pllout_clk_sys : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal sys_locked : std_logic;
signal local_reset_n : std_logic;
signal rst_n_sys : std_logic;
signal console_irq : std_logic;
signal hmq_in_irq : std_logic;
-- Mock Turtle
signal fmc_core_wb_out : t_wishbone_master_out_array(0 to 2);
signal fmc_core_wb_in : t_wishbone_master_in_array(0 to 2);
signal fmc_core_wb_out : t_wishbone_master_out_array(0 to 1);
signal fmc_core_wb_in : t_wishbone_master_in_array(0 to 1);
signal fmc_wb_muxed_out : t_wishbone_master_out;
signal fmc_wb_muxed_in : t_wishbone_master_in;
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- SPEC LEDs
signal led_divider : unsigned(22 downto 0);
signal leds : std_logic_vector(31 downto 0);
......@@ -368,63 +384,193 @@ begin
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CORE --
---------------------------------------------------------------------------------------------------
cmp_mock_turtle : spec_node_template
generic map
(g_simulation => g_simul,
g_with_wr_phy => false, -- no White Rabbit support, dah
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
g_system_clock_freq => 100000000, -- both CPUs at 100 MHz
g_wr_node_config => C_NODE_CONFIG)
cmp_reset_generator : entity work.spec_reset_gen
port map (
clk_sys_i => clk_100m_sys,
rst_pcie_n_a_i => l_rst_n_i,
rst_button_n_a_i => '1',
rst_n_o => local_reset_n);
cmp_buf_clk_pll : IBUFGDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => true -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10, --f_calc_sys_divider(100000000), -- 10
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys, -- 100 MHz
CLKOUT1 => open, --pllout_clk_cpu, -- 125 MHz
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_clk_sys_buf : BUFG
port map (
O => clk_100m_sys,
I => pllout_clk_sys);
cmp_mt_intercon : entity work.xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_100m_sys,
rst_n_i => local_reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
cmp_mock_turtle_urv: mock_turtle_core
generic map(
g_CONFIG => C_NODE_CONFIG,
g_SYSTEM_CLOCK_FREQ => 100000000, -- both CPUs at 100 MHz
g_WITH_WHITE_RABBIT => FALSE) -- no WR support
port map(
clk_i => clk_100m_sys, -- 100 MHz; one clk domain in the whole design
rst_n_i => local_reset_n, -- PCIe rst, synced with clk_sys
-- shared peripheral port: not used
-- dedicated (per-cpu) peripheral port
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o => fmc_core_wb_out, -- access from MT CPU0 and CPU1 at base address 0x100000
dp_master_i => fmc_core_wb_in,
host_slave_i => cnx_master_out(c_SLAVE_WR_NODE),
host_slave_o => cnx_master_in(c_SLAVE_WR_NODE),
hmq_in_irq_o => hmq_in_irq,
console_irq_o => console_irq);
U_VIC : entity work.xwb_vic
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 3,
g_init_vectors => c_VIC_VECTOR_TABLE,
g_retry_timeout => 10000) -- hack - 100us retry timeout to make SPEC work
port map (
clk_sys_i => clk_100m_sys,
rst_n_i => local_reset_n,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => '0',
irqs_i(1) => hmq_in_irq,
irqs_i(2) => console_irq,
irq_master_o => gpio_b(0));
cmp_GN4124_core : entity work.gn4124_core
port map
(clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
rst_n_sys_o => rst_n_sys, -- PCIe rst, synced with clk_sys
clk_sys_o => clk_100m_sys, -- 100 MHz; one clk domain in the whole design
-- PCIe interface
l_rst_n => l_rst_n_i,
gpio => gpio_b,
p2l_rdy => p2l_rdy_o,
p2l_clkn => p2l_clkn_i,
p2l_clkp => p2l_clkp_i,
p2l_data => p2l_data_i,
p2l_dframe => p2l_dframe_i,
p2l_valid => p2l_valid_i,
p_wr_req => p_wr_req_i,
p_wr_rdy => p_wr_rdy_o,
rx_error => rx_error_o,
l2p_data => l2p_data_o,
l2p_dframe => l2p_dframe_o,
l2p_valid => l2p_valid_o,
l2p_clkn => l2p_clkn_o,
l2p_clkp => l2p_clkp_o,
l2p_edb => l2p_edb_o,
l2p_rdy => l2p_rdy_i,
l_wr_rdy => l_wr_rdy_i,
p_rd_d_rdy => p_rd_d_rdy_i,
tx_error => tx_error_i,
vc_rdy => vc_rdy_i,
-- DAC interface
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
dac_cs1_n_o => dac_cs_n_o(0),
dac_cs2_n_o => dac_cs_n_o(1),
-- FMC presence
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_n_i,
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o(0) => fmc_core_wb_out(0), -- access from MT CPU0 at base address 0x100000
dp_master_o(1) => fmc_core_wb_out(1),
dp_master_i(0) => fmc_core_wb_in(0), -- access from MT CPU1 at base address 0x100000
dp_master_i(1) => fmc_core_wb_in(1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => fmc_core_wb_out(2), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => fmc_core_wb_in(2),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
clk_125m_gtp_n_i => '0',
clk_125m_gtp_p_i => '1');
( ---------------------------------------------------------
-- Control and status
rst_n_a_i => l_rst_n_i,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => p2l_clkp_i,
p2l_clk_n_i => p2l_clkn_i,
p2l_data_i => p2l_data_i,
p2l_dframe_i => p2l_dframe_i,
p2l_valid_i => p2l_valid_i,
-- P2L Control
p2l_rdy_o => p2l_rdy_o,
p_wr_req_i => p_wr_req_i,
p_wr_rdy_o => p_wr_rdy_o,
rx_error_o => rx_error_o,
vc_rdy_i => vc_rdy_i,
---------------------------------------------------------
-- L2P Direction
---------------------------------------------------------
-- Source Sync DDR related signals
l2p_clk_p_o => l2p_clkp_o,
l2p_clk_n_o => l2p_clkn_o,
l2p_data_o => l2p_data_o,
l2p_dframe_o => l2p_dframe_o,
l2p_valid_o => l2p_valid_o,
-- L2P Control
l2p_edb_o => l2p_edb_o,
l2p_rdy_i => l2p_rdy_i,
l_wr_rdy_i => l_wr_rdy_i,
p_rd_d_rdy_i => p_rd_d_rdy_i,
tx_error_i => tx_error_i,
---------------------------------------------------------
-- Interrupt interface
---------------------------------------------------------
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => open,
dma_reg_clk_i => clk_100m_sys,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_100m_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
-- csr_int_i => '0',
dma_clk_i => clk_100m_sys,
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0',
dma_dat_i => (others => '0'),
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_cyc_i => '0',
dma_reg_we_i => '0');
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
---------------------------------------------------------------------------------------------------
-- XBAR --
......@@ -435,7 +581,7 @@ begin
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note that in the MT firmware the CPU1 is only accessing the masterfip_leds register for debugging
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_wb_crossbar : xwb_crossbar
cmp_wb_crossbar : entity work.xwb_crossbar
generic map
(g_num_masters => 3,
g_num_slaves => 1,
......@@ -447,10 +593,10 @@ begin
rst_n_i => rst_n_sys,
slave_i(0) => fmc_core_wb_out(0),
slave_i(1) => fmc_core_wb_out(1),
slave_i(2) => fmc_core_wb_out(2),
slave_i(2) => cnx_master_out(c_SLAVE_FMC0),
slave_o(0) => fmc_core_wb_in(0),
slave_o(1) => fmc_core_wb_in(1),
slave_o(2) => fmc_core_wb_in(2),
slave_o(2) => cnx_master_in(c_SLAVE_FMC0),
master_o(0) => fmc_wb_muxed_out,
master_i(0) => fmc_wb_muxed_in);
......@@ -458,7 +604,7 @@ begin
---------------------------------------------------------------------------------------------------
-- FMC MASTERFIP CORE --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_core : fmc_masterFIP_core
cmp_masterFIP_core : entity work.fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
......@@ -502,7 +648,7 @@ begin
-- unused WISHBONE signals
fmc_wb_muxed_in.err <= '0';
fmc_wb_muxed_in.rty <= '0';
fmc_wb_muxed_in.int <= '0';
-- fmc_wb_muxed_in.int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
led_rx_act_n_o <= leds(0); -- probe on R4
......@@ -548,4 +694,4 @@ end rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
top/spec/spec_reset_gen.vhd 0 → 100644
View file @ 7afaf80f
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_reset_gen |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_reset_gen.vhd |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- SOLDERPAD LICENSE |
-- Copyright CERN 2014-2018 |
-- ------------------------------------ |
-- Copyright and related rights are licensed under the Solderpad Hardware License, Version 2.0 |
-- (the "License"); you may not use this file except in compliance with the License. |
-- You may obtain a copy of the License at http://solderpad.org/licenses/SHL-2.0. |
-- Unless required by applicable law or agreed to in writing, software, hardware and materials |
-- distributed under this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR |
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language |
-- governing permissions and limitations under the License. |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
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