Skip to content

M
MasterFIP - Gateware
Commit 70eae2d0 authored by kblantos's avatar kblantos
Browse files
Options

Changed wf_package to wf_mfp_package in order not to have a conflict with wf_package from nanofip

parent c71620d0
Hide whitespace changes
Inline Side-by-side
Showing with 269 additions and 33 deletions
rtl/Manifest.py
View file @ 70eae2d0
......@@ -7,7 +7,7 @@ files = [
"masterfip_tx.vhd",
"masterfip_wbgen2_csr.vhd",
"masterfip_wbgen2_pkg.vhd",
"wf_package.vhd",
"wf_mfp_package.vhd",
"spi_slave.vhd",
"mt_profip_translator.vhd",
]
......
rtl/fmc_masterFIP_core.vhd
View file @ 70eae2d0
......@@ -156,7 +156,7 @@ use work.masterfip_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
-- Entity declaration for fmc_masterFIP_core
......
rtl/masterFIP_pkg.vhd
View file @ 70eae2d0
......@@ -14,8 +14,8 @@
-- |
-- Description Definitions of constants, types, entities related to the interface between the |
-- fmc_masterfip_core and the Mock Turtle. |
-- Note that a different package, the wf_package, is used for the WorldFIP specific |
-- constant, types, entities and for the clock constants. |
-- Note that a different package, the wf_mfp_package, is used for the WorldFIP |
-- specific constant, types, entities and for the clock constants. |
-- |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- |
......@@ -43,7 +43,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wf_package.all; -- WorldFIP specifics package
use work.wf_mfp_package.all;
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
......
rtl/masterfip_rx.vhd
View file @ 70eae2d0
......@@ -97,8 +97,7 @@ use IEEE.math_real.all;
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
-- Entity declaration for masterfip_rx
......
rtl/masterfip_tx.vhd
View file @ 70eae2d0
......@@ -96,8 +96,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
use work.wf_mfp_package.all;
--=================================================================================================
-- Entity declaration for masterfip_tx
......
rtl/spi_slave_old.vhd 0 → 100644
View file @ 70eae2d0
-------------------------------------------------------------------------------
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : SPI Slave
-- Project : ProFIP
-------------------------------------------------------------------------------
-- File : spi_slave.vhd
-- Author : Konstantinos Blantos
-- Company : CERN (BE-CEM-EDL)
-- Created : 13-10-2022
-- Last update:
-- Platform : FPGA-generic
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Simple SPI Slave. Receiving input data in any given width
-- and sending to a master through MISO. Receiving MOSI bits and
-- converting it to output data. Control signals also supported.
-------------------------------------------------------------------------------
-- Copyright (c) 2019 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
--=============================================================================
-- Libraries & Packages --
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for spi_slave --
--=============================================================================
entity spi_slave is
generic (
g_data_width : natural; -- Data width in bits
g_cpol : natural range 0 to 1; -- Clock polarity (can be 0 or 1)
g_cpha : natural range 0 to 1 -- Clock phase (can be 0 or 1)
);
port (
-- FPGA clock and reset
clk_i : in std_logic; -- System (wishbone) clock
rst_n_i : in std_logic; -- System (wishbone) reset
-- SPI Interface
spi_clk_i : in std_logic; -- SPI clock
spi_cs_n_i : in std_logic; -- SPI chip select, active LOW
spi_mosi_i : in std_logic; -- SPI serial data, master out slave in
spi_miso_o : out std_logic; -- SPI serial data, master in slave out
-- User Interface
data_i : in std_logic_vector(g_data_width-1 downto 0);
data_valid_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
data_valid_o : out std_logic;
-- Flag
busy_o : out std_logic;
ready_o : out std_logic
);
end entity spi_slave;
--==============================================================================
-- Architecture declaration --
--==============================================================================
architecture rtl of spi_slave is
-- Returns log of 2 of a natural number
function f_log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + f_log2_ceil(N/2);
else
return 1 + f_log2_ceil((N+1)/2);
end if;
end;
--! Reset
signal s_rst_n : std_logic;
-- Signals
signal data_reg_o : std_logic_vector(g_data_width-1 downto 0);
signal data_reg_i : std_logic_vector(g_data_width-1 downto 0);
signal mosi_cnt : unsigned(f_log2_ceil(g_data_width)-1 downto 0);
signal miso_cnt : unsigned(f_log2_ceil(g_data_width)-1 downto 0);
signal s_data_valid : std_logic;
signal spi_clk_sync : std_logic;
signal spi_clk_redge : std_logic;
signal spi_clk_fedge : std_logic;
signal spi_cs_n_sync : std_logic;
signal sample_en : std_logic;
signal shift_en : std_logic;
signal mosi : std_logic;
signal s_ready : std_logic;
begin
----------------------------------------------------------------------------
-- Synchronize signals from SPI to the clock domain of FPGA
----------------------------------------------------------------------------
-- Use of gc_sync_ffs module in order to synchronize and
-- detect the negative and positive edges of clock
-- Here spi clock can be 0.5MHz up to 25MHz
-- and FPGA clk_i should be 62.5MHz or 100MHz/125MHz
cmp_spi_clk_sync_ffs : entity work.gc_sync_ffs
generic map (
g_SYNC_EDGE => "positive"
)
port map (
clk_i => clk_i, -- clock from the destination clock domain (125MHz)
rst_n_i => rst_n_i, -- async reset
data_i => spi_clk_i, -- async input
synced_o => spi_clk_sync, -- synchronized output
npulse_o => spi_clk_fedge, -- negative edge detect output
ppulse_o => spi_clk_redge -- positive edge detect output
);
-- Define the sampling and shifting based on the CPHA
gen_pha_zero : if g_cpha = 0 generate
sample_en <= spi_clk_redge;
shift_en <= spi_clk_fedge;
end generate;
gen_pha_one : if g_cpha = 1 generate
sample_en <= spi_clk_fedge;
shift_en <= spi_clk_redge;
end generate;
cmp_spi_cs_n_sync_ffs : entity work.gc_sync_ffs
generic map (
g_SYNC_EDGE => "positive"
)
port map (
clk_i => clk_i, -- clock from the destination clock domain (125MHz)
rst_n_i => rst_n_i, -- async reset
data_i => spi_cs_n_i, -- async input
synced_o => spi_cs_n_sync, -- synchronized output
npulse_o => open, -- negative edge detect output
ppulse_o => open -- positive edge detect output
);
cmp_spi_mosi_sync_ffs : entity work.gc_sync_ffs
generic map (
g_SYNC_EDGE => "positive"
)
port map (
clk_i => clk_i, -- clock from the destination clock domain (125MHz)
rst_n_i => rst_n_i, -- async reset
data_i => spi_mosi_i, -- async input
synced_o => mosi, -- synchronized output
npulse_o => open, -- negative edge detect output
ppulse_o => open -- positive edge detect output
);
----------------------------------------------------------------------------
-- RTL logic for Sampling and Shifting MOSI/MISO data bits
----------------------------------------------------------------------------
--! Reset
s_rst_n <= rst_n_i and not(spi_cs_n_sync);
----------------------------------------------------------------------------
-- MOSI
----------------------------------------------------------------------------
-- Process to sample the MOSI data
p_MOSI : process(clk_i, s_rst_n)
begin
if s_rst_n = '0' then
data_reg_o <= (others=>'0');
mosi_cnt <= (others=>'0');
s_data_valid <= '0';
elsif rising_edge(clk_i) then
if sample_en = '1' then
data_reg_o <= data_reg_o(g_data_width-2 downto 0) & mosi;
if (mosi_cnt = g_data_width-1) then
s_data_valid <= '1';
mosi_cnt <= (others=>'0');
else
s_data_valid <= '0';
mosi_cnt <= mosi_cnt + 1;
end if;
end if;
end if;
end process p_MOSI;
data_o <= data_reg_o;
data_valid_o <= s_data_valid;
----------------------------------------------------------------------------
-- MISO
----------------------------------------------------------------------------
p_MISO : process(clk_i, s_rst_n)
begin
if s_rst_n = '0' then
data_reg_i <= (others=>'0');
miso_cnt <= (others=>'0');
s_ready <= '0';
elsif rising_edge(clk_i) then
if shift_en = '1' then
if g_cpha = 1 and miso_cnt = 0 then
data_reg_i <= data_i;
miso_cnt <= miso_cnt + 1;
s_ready <= '0';
else
data_reg_i <= data_reg_i(g_data_width-2 downto 0) & '0';
if miso_cnt = g_data_width-1 then
miso_cnt <= (others=>'0');
s_ready <= '1';
else
miso_cnt <= miso_cnt + 1;
s_ready <= '0';
end if;
end if;
end if;
end if;
end process p_MISO;
spi_miso_o <= data_reg_i(g_data_width-1);
ready_o <= s_ready;
end architecture rtl;
rtl/wf_package.vhd → rtl/wf_mfp_package.vhd
View file @ 70eae2d0
......@@ -7,16 +7,16 @@
---------------------------------------------------------------------------------------------------
-- |
-- wf_package |
-- wf_mfp_package |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_package.vhd |
-- File wf_mfp_package.vhd |
-- |
-- Description Definitions of constants, types, entities, functions related to WorldFIP |
-- serialization and deserialization; the package is essential for all the modules |
-- coming from the nanoFIP design. |
-- As in the masterFIP design the clk is 100 MHz and in the nanoFIP 40 MHz it was |
-- necessary to have a new wf_package. In principle the nanoFIP design could have |
-- necessary to have a new wf_mfp_package. In principle the nanoFIP design could have|
-- been modified to accept generics rather than constants, however as it is a stable |
-- design it was decided to keep it as it is and use for synthesis this package |
-- rather than the one coming with the nanoFIP submodule. |
......@@ -53,10 +53,9 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Package declaration for wf_package
-- Package declaration for wf_mfp_package
--=================================================================================================
package wf_package is
package wf_mfp_package is
---------------------------------------------------------------------------------------------------
-- Constants regarding the system clock --
......@@ -387,14 +386,12 @@ end component wf_rx_osc;
end wf_package;
end wf_mfp_package;
--=================================================================================================
-- package body
--=================================================================================================
package body wf_package is
package body wf_mfp_package is
---------------------------------------------------------------------------------------------------
-- Function for the encoding of a word to its Manchester 2 (manch.) equivalent.
......@@ -420,7 +417,7 @@ package body wf_package is
end wf_package;
end wf_mfp_package;
--=================================================================================================
-- package end
--=================================================================================================
......
testbench/top_mt/main.sv
View file @ 70eae2d0
......@@ -59,14 +59,14 @@ module main;
)
DUT (
// Clock, Reset
.rst_n_i (rst_n),
.clk_125m_pllref_p_i(clk_sys),
.clk_125m_pllref_n_i(~clk_sys),
.rst_n_i (rst_n),
.clk_125m_pllref_p_i (clk_sys),
.clk_125m_pllref_n_i (~clk_sys),
// ERTEC SPI Interface
.ertec_spi_clk_i (spi_clk),
.ertec_spi_mosi_i (spi_mosi),
.ertec_spi_cs_n_i (spi_cs_n),
.ertec_spi_miso_o (spi_miso),
.ertec_spi_clk_i (spi_clk),
.ertec_spi_mosi_i (spi_mosi),
.ertec_spi_cs_n_i (spi_cs_n),
.ertec_spi_miso_o (spi_miso),
// VME Interface
.vme_sysreset_n_i (VME_RST_n),
.vme_as_n_i (VME_AS_n),
......@@ -346,8 +346,9 @@ module main;
@(posedge spi_clk);
spi_mosi = mosi_data[i-1];
end
*/
@(posedge spi_clk);
*/
endtask // sending_second_from_ertec()
task sending_third_from_ertec();
......@@ -483,7 +484,7 @@ module main;
$display("**** Starting the 5th frame like ERTEC ****");
mosi_data = 'h00010400; // Basic Info
mosi_data = 'h00060400; // Basic Info
for (i=32;i>0;i--)
begin
@(posedge spi_clk);
......@@ -561,7 +562,7 @@ module main;
$display("**** Starting the 6th frame like ERTEC ****");
mosi_data = 'h01010200; // Basic Info
mosi_data = 'h01060200; // Basic Info
for (i=32;i>0;i--)
begin
@(posedge spi_clk);
......@@ -654,7 +655,12 @@ module main;
else
posedge_cnt <= posedge_cnt + 1;
end
// Checks that MOSI data is as expected
always @(posedge clk_sys)
begin
end
initial begin
automatic MockTurtleDriver drv;
......
top/svec/svec_masterfip_mt_urv.vhd
View file @ 70eae2d0
......@@ -338,7 +338,7 @@ architecture rtl of svec_masterfip_mt_urv is
cpu_config => (0 => (memsize => 28672, --90760, -- in words(0x16288); the size should be enough for the storage of the RT sw running on CPU0 and for the macrocycle configuration
hmq_config => (1, (others => (2, 7, 2, x"0000_0000", true))), -- 4 entries, 128 wide, 2 header bits
rmq_config => (6, (others => (2, 7, 3, x"0000_0000", true)))), --(c_DUMMY_MT_MQUEUE_SLOT)))),
1 => (memsize => 2084, --0x00824,
1 => (memsize => 3072, --uint_8: 12288 --2084, --0x00824,
hmq_config => (1, (others => (2, 7, 2, x"0000_0000", true))),
rmq_config => (1, (others => (2, 7, 3, x"0000_0000", true)))), --(c_DUMMY_MT_MQUEUE_SLOT)))),
others => (0, c_MT_DEFAULT_MQUEUE_CONFIG, c_MT_DEFAULT_MQUEUE_CONFIG)),
......@@ -532,7 +532,7 @@ begin
rmq_endpoint_in.snk_in(0)(5) <= rmq_src_out;
rmq_endpoint_in.src_in(0)(5) <= rmq_snk_out(0)(5);
when x"08" =>
when x"06" =>
rmq_src_in <= rmq_endpoint_out.snk_out(1)(0);
rmq_endpoint_in.snk_in(1)(0) <= rmq_src_out;
rmq_endpoint_in.src_in(1)(0) <= rmq_snk_out(1)(0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment