New approach for mt_profip_translator. Everything in one module. Simulation fine. HW test needed

6ac8bf43 · kblantos · 340c2a13 · 6ac8bf43 · 6ac8bf43 · 6ac8bf43
Commit 6ac8bf43 authored Mar 05, 2023 by kblantos
5 changed files
--- a/rtl/mt_profip_translator.vhd
+++ b/rtl/mt_profip_translator.vhd
--- a/rtl/spi_slave.vhd
+++ b/rtl/spi_slave.vhd
@@ -27,6 +27,8 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+use work.gencores_pkg.all;
+
 --=============================================================================
 --                       Entity declaration for spi_slave                    --
 --=============================================================================
@@ -64,18 +66,6 @@ end entity spi_slave;

 architecture rtl of spi_slave is

-    -- Returns log of 2 of a natural number
-    function f_log2_ceil(N : natural) return positive is
-    begin
-        if N <= 2 then
-            return 1;
-        elsif N mod 2 = 0 then
-            return 1 + f_log2_ceil(N/2);
-        else
-            return 1 + f_log2_ceil((N+1)/2);
-        end if;
-    end;
-
    --! Reset
    signal s_rst_n          : std_logic;

@@ -184,7 +174,7 @@ begin
        end if;
    end process p_MOSI;

-    data_o  <= data_reg_o;
+    data_o       <= data_reg_o;
    data_valid_o <= s_data_valid;

    operation_o <= data_reg_o(0) when mosi_cnt = 8 else '0';

--- a/testbench/top_mt/main.sv
+++ b/testbench/top_mt/main.sv
--- a/testbench/top_mt/wave.do
+++ b/testbench/top_mt/wave.do
--- a/top/svec/svec_masterfip_mt_urv.vhd
+++ b/top/svec/svec_masterfip_mt_urv.vhd