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MasterFIP - Gateware
Commit 30aa75bc authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- now providing to MT the current number of words rather than of bytes… 

- now providing to MT the current number of words rather than of bytes (rx_words_indx rather than rx_byte_indx)
- updated simulations
parent 88588a39
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Showing with 444 additions and 323 deletions
rtl/fmc_masterFIP_core.vhd
View file @ 30aa75bc
......@@ -232,7 +232,8 @@ architecture rtl of fmc_masterFIP_core is
signal rx_crc_wrong_p, rx_crc_wrong, rx_byte_ready_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_bytes_num : std_logic_vector(15 downto 0);
signal rx_byte_index, rx_bytes_num, rx_word_index : std_logic_vector(15 downto 0);
signal rx_word_index_tmp : std_logic_vector(6 downto 0);
-- fd_wdgn, fd_txer
signal fd_wdg_tstamp, fd_txer_tstamp : std_logic_vector(30 downto 0);
signal fd_wdg_sync, fd_wdg, fd_wdg_act : std_logic;
......@@ -300,8 +301,8 @@ begin
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
-- resets
mf_rst_core_o => core_host_rst_p, -- 1-clk-tick-long pulse
mf_rst_fd_o => fd_host_rst_p, -- 1-clk-tick-long pulse
mf_rst_core_o => core_host_rst_p, -- monostable: 1-clk-tick-long pulse
mf_rst_fd_o => fd_host_rst_p, -- monostable: 1-clk-tick-long pulse
--dbg
mf_dbg_o => mf_dbg,
-- adc supplies
......@@ -319,7 +320,7 @@ begin
mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
-- DAC configuration
mf_dac_config_value_o => dac_value,
mf_dac_config_load_o => dac_load_p, -- 1-clk-tick-long pulse
mf_dac_config_load_o => dac_load_p, -- monostable: 1-clk-tick-long pulse
-- bus speed
mf_speed_i(1) => speed_b1_i,
mf_speed_i(0) => speed_b0_i,
......@@ -328,16 +329,16 @@ begin
mf_macrocyc_num_cnt_i => num_of_macrocyc_cnt,
mf_turnar_lgth_o => turnar_lgth,
mf_silen_lgth_o => silen_lgth,
mf_macrocyc_start_o => macrocyc_host_load_p, -- 1-clk-tick-long pulse
mf_turnar_start_o => turnar_host_load_p, -- 1-clk-tick-long pulse
mf_silen_start_o => silen_host_load_p, -- 1-clk-tick-long pulse
mf_macrocyc_start_o => macrocyc_host_load_p, -- monostable: 1-clk-tick-long pulse
mf_turnar_start_o => turnar_host_load_p, -- monostable: 1-clk-tick-long pulse
mf_silen_start_o => silen_host_load_p, -- monostable: 1-clk-tick-long pulse
-- counters inputs
mf_macrocyc_time_cnt_i => macrocyc_cnt,
mf_turnar_time_cnt_i => turnar_cnt,
mf_silen_time_cnt_i => silen_cnt,
-- tx control
mf_tx_ctrl_rst_o => tx_host_rst_p, -- 1-clk-tick-long pulse
mf_tx_ctrl_start_o => tx_start_p, -- 1-clk-tick-long pulse; tx start serializing a frame
mf_tx_ctrl_rst_o => tx_host_rst_p, -- monostable: 1-clk-tick-long pulse
mf_tx_ctrl_start_o => tx_start_p, -- monostable: 1-clk-tick-long pulse; tx start serializing a frame
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start
-- tx status
mf_tx_stat_stop_i => tx_completed, -- stays active until a tx_rst or core_rst or tx_start_p
......@@ -357,7 +358,8 @@ begin
mf_rx_stat_frame_crc_err_i => rx_crc_wrong,
mf_rx_stat_bytes_num_i => rx_bytes_num, -- number of bytes to read from the rx_frame upon rx_frame_ok
-- counting starts after the FSS; includes CTRL, Data, CRC, FES fields
mf_rx_stat_curr_byte_indx_i => rx_byte_index, -- current byte being deserialized
mf_rx_stat_curr_byte_indx_i => rx_word_index, --rx_byte_index, -- current byte being deserialized
-- counting starts after the FSS; includes CTRL, data, CRC, FES fields
-- rx data
mf_rx_data_ctrl_i => rx_ctrl_byte,
......@@ -506,7 +508,6 @@ begin
ext_sync_tst_n_o <= '0' when ext_sync_tst_n = '0' else 'Z';
---------------------------------------------------------------------------------------------------
-- resets --
---------------------------------------------------------------------------------------------------
......@@ -641,7 +642,7 @@ begin
-- counter counting the silence time i.e. the maximum amount of time that the masterFIP waits for
-- a response frame; the counting starts after the transmission of a frame sent by the master
-- (tx_completed_p) or after the reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p) for the
-- case of a RP_DAT_MSG that would be followed by P_FIN.
-- case of a RP_DAT_MSG that would be followed by RP_FIN.
cmp_silence_cnt: decr_counter
generic map(width => 31)
......@@ -672,12 +673,12 @@ begin
else
if rx_frame_ok_p = '1' then
rx_frame_ok <= rx_frame_ok_p;
rx_bytes_num <= rx_byte_index;
rx_bytes_num <= rx_byte_index - 3; -- actual payload, without FSS, CTRL, CRC, FES bytes
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extending the rx_fss_received_p until a core_rst or rx_rst is received
p_rx_fss_received_extend : process(clk_i)
......@@ -721,6 +722,7 @@ begin
-------------------------------------------------------------
rx_byte_index_o => rx_byte_index, -- current amount of bytes (counting starts after the fss;
-- includes ctrl, data, crc, fes fields)
rx_word_index_o => rx_word_index_tmp,
rx_ctrl_byte_o => rx_ctrl_byte,
rx_frame_o => rx_frame,
rx_byte_o => rx_byte,
......@@ -730,7 +732,7 @@ begin
rx_crc_wrong_p_o => rx_crc_wrong_p);
-------------------------------------------------------------
rx_word_index <= "000000000" & rx_word_index_tmp;
---------------------------------------------------------------------------------------------------
-- tx --
---------------------------------------------------------------------------------------------------
......@@ -904,7 +906,7 @@ begin
-- drivers. Note that a temperature reading is provided every second, with the first one a couple
-- of sec after the board power-up/ reset.
cmp_onewire: onewire_interf
cmp_onewire: onewire_interf --gc_ds182x_interface
generic map (freq => 100)
port map
(clk_i => clk_i,
......@@ -972,10 +974,10 @@ begin
aux_o(6) <= mf_dbg_p_ext;
aux_o(5) <= mf_dbg(5);
aux_o(4) <= mf_dbg(4); --rx_byte_ready_p;
aux_o(3) <= mf_dbg(3); --macrocyc_cnt_zero_p;
aux_o(2) <= mf_dbg(2); --tx_completed;
aux_o(1) <= mf_dbg(1); --tx_start;
aux_o(0) <= mf_dbg(0); --sync_led;
aux_o(3) <= rx_fss_received_p;--mf_dbg(3); --macrocyc_cnt_zero_p;
aux_o(2) <= rx_frame_ok_p;--(2); --tx_completed;
aux_o(1) <= tx_completed_p;--mf_dbg(1); --tx_start;
aux_o(0) <= silen_load_p;--mf_dbg(0); --sync_led;
ext_sync_oe_o <= ext_sync_oe;
......
rtl/masterFIP_pkg.vhd
View file @ 30aa75bc
......@@ -514,6 +514,7 @@ end component;
rx_rst_i : in std_logic;
-----------------------------------------------------------------
rx_byte_index_o : out std_logic_vector (15 downto 0);
rx_word_index_o : out std_logic_vector (6 downto 0);
rx_ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_frame_o : out rx_frame_t;
rx_byte_o : out std_logic_vector (7 downto 0);
......
rtl/masterfip_rx.vhd
View file @ 30aa75bc
......@@ -84,6 +84,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use IEEE.math_real.all;
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
......@@ -119,6 +120,8 @@ entity masterfip_rx is port(
-- CTRL, DATA, CRC and FES fields;
-- normally the value should not exceed 266
rx_word_index_o : out std_logic_vector(6 downto 0); -- index of the word ...
rx_ctrl_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_frame_o : out rx_frame_t; -- frame DATA bytes
......@@ -155,7 +158,6 @@ architecture struc of masterfip_rx is
signal rx_byte : std_logic_vector (7 downto 0);
-- retrieved bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0');
signal word32 : std_logic_vector(31 downto 0);
signal word32_num : integer range 0 to 66;
-- bytes counter
signal rx_byte_index, rx_byte_index_d1 : unsigned(15 downto 0) := (others => '0');
......@@ -230,7 +232,7 @@ begin
cmp_rx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 16) -- normally max frame size = 268 bytes which would fit in 9 bits;
-- more bits have been added to be able to detect if the
-- serializer is by mistake continuing acquiring bytes;
-- deserializer is by mistake continuing acquiring bytes;
-- note: the 83ms time-out of the deserializer unit, translates to
-- up to 26000 bytes at the fastest speed 2.5Mbps
port map(
......@@ -271,7 +273,6 @@ begin
end if;
end if;
end process;
-------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -302,28 +303,23 @@ begin
else
if rx_fss_crc_fes_ok_p = '1' then
if (rx_byte_index-2) mod 4 = 0 or (rx_byte_index-2) mod 4 = 3 then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
elsif (rx_byte_index-2) mod 4 = 2 then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= "00000000" & byte0 & byte1 & byte2;--std_logic_vector(srl (unsigned(byte0 & byte1 & byte2 & byte3), 8));
else
-- upon rx_fss_crc_fes_ok_p, the last 32bit word will contain for sure CRC0, CRC1 and FES
-- and it may also contain up to one byte of data.
if (rx_byte_index-3) mod 4 = 1 then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= "0000000000000000" & byte0 & byte1;-- std_logic_vector(srl (unsigned(byte0 & byte1 & byte2 & byte3), 16));
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; -- byte3 is the data byte; the other ones can be "0"
end if;
elsif (rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0) then
elsif (rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0) then -- for all the other bytes
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
end if;
end if;
end if;
end process;
rx_word_index_o <= std_logic_vector(to_unsigned(word32_num,7));
end architecture struc;
--=================================================================================================
......
sim/spec/data_vectors/board_settings_config.txt
View file @ 30aa75bc
......@@ -7,8 +7,8 @@ sd1 -- m_id_2 can take the values (gnd, vcc, sd0, sd1)
sd0 -- m_id_1 can take the values (gnd, vcc, sd0, sd1)
vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1)
1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1)
000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
001 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10)
1 -- mode (slone): memory mode(0), stand alone(1)
0 -- mode (slone): memory mode(0), stand alone(1)
03 -- station_adr (8-bit bus in hexadecimal format)
20000 ms -- time for which the configuration above is valid
sim/spec/data_vectors/masterFIP_test.vec
View file @ 30aa75bc
......@@ -90,12 +90,15 @@ wr 000000000003016C F 00000002
wait %d20
-- data bytes
wr 0000000000030170 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wr 0000000000030170 F BBAA0940 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wr 0000000000030174 F FFEEDDCC -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wait %d20
wr 0000000000030178 F 00052B1A -- for 2 data bytes: 00000000 | for 8 data bytes: 00052B1A
wait %d20
wr 0000000000030174 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
-- tx_start
wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wr 000000000003003C F 00000B02 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wait %d20000
wr 000000000003003C F 00000000
wait %d20000
......@@ -113,7 +116,7 @@ wr 000000000003016C F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030170 F 00000306 -------------------------0314
wr 0000000000030170 F 00000314 -------------------------0314
wait %d20
-- tx_start
......@@ -145,7 +148,7 @@ wr 000000000003016C F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030168 F 00000306
wr 0000000000030170 F 00000306
wait %d20
-- tx_start
......
sim/spec/data_vectors/user_sequence.txt
View file @ 30aa75bc
## Sequence of Wishbone transfers separated by stand-by times. The transfer parameters must be separated by comas, without spaces.
## The order and values must be as follows: rd_wr: (0) for read / (1) for write, variable: (1) for consumed / (2) for broadcast / (3) for produced,
## data transfer size: integer from 1 to 124, transfer offset: integer from 1 to 124, transfer block size: integer from 1 to 124.
350 us -- stand-by time
270 us -- stand-by time
0,1,8,0,0 -- reading VAR1 from memory
350 us -- stand-by time
1,3,8,0,0 -- writting VAR3 in memory
50 us -- stand-by time
1,3,8,0,8 -- writting VAR3 in memory
20383 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
......
sim/spec/testbench/tb_masterFIP.vhd
View file @ 30aa75bc
......@@ -231,6 +231,7 @@ end component;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
rstpon_o : out std_logic;
uclk_o : out std_logic;
......@@ -536,7 +537,7 @@ begin
ack_o => ack,
adr_i => adr,
cyc_i => cyc,
dat_i => "0101010101010111",--dat_to_fip,
dat_i => dat_to_fip,
dat_o => dat_from_fip,
stb_i => stb,
we_i => we,
......@@ -567,6 +568,8 @@ begin
var1_rdy_i => var1_rdy,
var2_rdy_i => var2_rdy,
var3_rdy_i => var3_rdy,
p3_lgth_i => p3_lgth,
var1_acc_o => var1_acc,
var2_acc_o => var2_acc,
var3_acc_o => var3_acc,
......
sim/spec/testbench/user_interface.vhd
View file @ 30aa75bc
......@@ -16,7 +16,8 @@ entity user_interface is
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
p3_lgth_i : in std_logic_vector(2 downto 0);
rstpon_o : out std_logic;
uclk_o : out std_logic;
urstn_to_nf : out std_logic;
......@@ -68,6 +69,13 @@ architecture archi of user_interface is
port(
uclk_period : in time;
wclk_period : in time;
wclk_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
p3_lgth_i : in std_logic_vector(2 downto 0);
block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
......@@ -185,6 +193,7 @@ begin
uclk <= not(uclk);
wait for uclk_period/2;
end process;
user_reset: process
begin
......@@ -277,11 +286,18 @@ begin
ureset => ureset,
var_id => var_id
);
user_sequence: user_sequencer
user_sequence: user_sequencer
port map(
uclk_period => uclk_period,
wclk_period => wclk_period,
wclk_i => wclk,
var1_rdy_i => var1_rdy_i,
var2_rdy_i => var2_rdy_i,
var3_rdy_i => var3_rdy_i,
p3_lgth_i => p3_lgth_i,
block_size => block_size,
launch_slone_read => launch_slone_read,
......@@ -293,6 +309,7 @@ begin
var_id => var_id
);
user_acc_monitor: user_access_monitor
port map(
cyc => cyc,
......
sim/spec/testbench/user_sequencer.vhd
View file @ 30aa75bc
This diff is collapsed.
sim/spec/testbench/wishbone_interface.vhd
View file @ 30aa75bc
......@@ -8,6 +8,7 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.NUMERIC_STD.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
......@@ -71,6 +72,7 @@ signal stb : std_logic;
signal valid_bus_cycle : std_logic;
signal var_adr : std_logic_vector(1 downto 0):=(others=>'0');
signal we : std_logic:='0';
signal in_consumed : vector_type;
begin
......@@ -98,7 +100,7 @@ begin
reset_mem <= '1';
stb <= '0';
if (launch_wb_read /='0' or launch_wb_write /='0') then
if (launch_wb_read ='1' or launch_wb_write ='1') then
if burst_size > zero then
nxt_wb_state <= burst;
else
......@@ -177,7 +179,7 @@ begin
mem_length <= transfer_length - ("000" & x"1");
mem_offset <= transfer_offset + ("000" & x"2");
end if;
var_adr <= var_id -"01";
var_adr <= "00";--var_id -"01";
we <= '0';
elsif launch_wb_write ='1' then
if block_size = zero then
......@@ -187,7 +189,7 @@ begin
end if;
mem_length <= transfer_length - ("000" & x"1");
mem_offset <= transfer_offset + ("000" & x"2");
var_adr <= var_id -"01";
var_adr <= "10";--var_id -"01"; -- only consumed, not broadcast consumed
we <= '1';
end if;
end process;
......@@ -199,23 +201,57 @@ begin
-----------------------
adr_o <= add_count;
cyc_o <= cyc;
dat_o <= data_for_mem;
dat_o <= in_consumed(to_integer(unsigned(mem_length - mem_count)));--data_for_mem;
stb_o <= stb;
we_o <= we;
-- process reading bytes from random data file
-- process reading bytes ...........from the bytes consumed
---------------------------------------------
read_store: process
file data_file: text open read_mode is "../../sim/spec/data_vectors/data_store.txt";
variable data_line: line;
variable data_byte: std_logic_vector(7 downto 0);
-- read_store: process
-- file data_file_tmp1_rd : text open read_mode is "../../sim/spec/data_vectors/tmp_var1_mem.txt";
-- variable data_line: line;
-- variable data_byte: std_logic_vector(7 downto 0);
-- begin
-- if stb = '1' and cyc = '1' and we = '1' then
-- readline (data_file_tmp1_rd, data_line);
-- hread (data_line, data_byte);
-- data_for_mem <= data_byte;
--file_close(data_file);
-- end if;
-- wait until clk_i ='1';
-- end process;
--process reading from a text file the data sent by FIP for consumption
--------------------------------------------------------------------
read_incoming_data: process(launch_wb_write)
file data_file_tmp1_rd : text open read_mode is "../../sim/spec/data_vectors/tmp_var1_mem.txt";
variable data_line : line;
variable data_byte : std_logic_vector(7 downto 0);
variable data_vector : vector_type;
variable i : integer:=0;
begin
readline (data_file, data_line);
hread (data_line, data_byte);
data_for_mem <= data_byte;
wait until clk_i ='1';
end process;
data_vector := (others => x"00");
if launch_wb_write = '1' then
report " eeeeeeeeeeeeeentering!!!";
while not(endfile(data_file_tmp1_rd)) loop
report " reading line!!!";
readline (data_file_tmp1_rd, data_line);
report " reading line!!!";
hread (data_line, data_byte);
data_vector(i) := data_byte;
i := i+1;
report "lalalalalala #" & Integer'image(i);
end loop;
file_close(data_file_tmp1_rd);
i := 0;
in_consumed <= data_vector;
end if;
end process;
burst_counter: encounter
generic map(
width => 7
......
sim/spec/testbench/wishbone_monitor.vhd
View file @ 30aa75bc
......@@ -44,57 +44,66 @@ begin
-- process reading from a text file the data sent by FIP for consumption
------------------------------------------------------------------------
read_incoming: process(cyc_o, var_id)
file data_file : text;
variable data_line : line;
variable data_byte : std_logic_vector(7 downto 0);
variable data_vector : vector_type;
variable i : integer:=0;
-- read_incoming: process(cyc_o, var_id)
-- file data_file : text;
-- variable data_line : line;
-- variable data_byte : std_logic_vector(7 downto 0);
-- variable data_vector : vector_type;
-- variable i : integer:=0;
begin
if cyc_o ='1' then
if var_id = 1 then
data_vector := (others => x"00");
file_open(data_file,"../../sim/spec/data_vectors/tmp_var1_mem.txt",read_mode);
while not(endfile(data_file)) loop
readline (data_file, data_line);
hread (data_line, data_byte);
data_vector(i) := data_byte;
i := i+1;
end loop;
file_close(data_file);
i := 0;
in_consumed <= data_vector;
-- begin
-- if cyc_o ='1' then
-- if var_id = 1 then
-- data_vector := (others => x"00");
-- file_open(data_file,"../../sim/spec/data_vectors/tmp_var1_mem.txt",read_mode);
-- while not(endfile(data_file)) loop
-- readline (data_file, data_line);
-- hread (data_line, data_byte);
-- data_vector(i) := data_byte;
-- i := i+1;
-- end loop;
-- file_close(data_file);
-- i := 0;
-- in_consumed <= data_vector;
elsif var_id = 2 then
data_vector := (others => x"00");
file_open(data_file,"../../sim/spec/data_vectors/tmp_var2_mem.txt",read_mode);
while not(endfile(data_file)) loop
readline (data_file, data_line);
hread (data_line, data_byte);
data_vector(i) := data_byte;
i := i+1;
end loop;
file_close(data_file);
i := 0;
in_broadcast <= data_vector;
end if;
end if;
end process;
-- elsif var_id = 2 then
-- data_vector := (others => x"00");
-- file_open(data_file,"../../sim/spec/data_vectors/tmp_var2_mem.txt",read_mode);
-- while not(endfile(data_file)) loop
-- readline (data_file, data_line);
-- hread (data_line, data_byte);
-- data_vector(i) := data_byte;
-- i := i+1;
-- end loop;
-- file_close(data_file);
-- i := 0;
-- in_broadcast <= data_vector;
-- end if;
-- end if;
-- end process;
-- process checking the validity of the incoming consumed data as they are retrieved from nanoFIP memory
-- process checking the incoming consumed data as they are retrieved from nanoFIP memory
--------------------------------------------------------------------------------------------------------
check_consumed_and_broadcast: process
variable data_line_tmp1 : line;
file data_file_tmp1 : text open write_mode is "../../sim/spec/data_vectors/tmp_var1_mem.txt";
begin
if valid_bus_cycle then
if valid_bus_cycle and we_o = '0' then
if var_id = 1 then
if in_consumed(adr) /= dat_i then
report LF & " #### check NOT OK #### Value retrieved from memory DAT_I::::" & integer'image(to_integer(unsigned(dat_i))) &
"in address " & integer'image(adr) &
" of the Consumed variable does not match the corresponding one sent from FIP by the BA" & LF
severity warning;
errct_trig <= '1';
end if;
hwrite (data_line_tmp1, dat_i);
writeline (data_file_tmp1, data_line_tmp1);
--if in_consumed(adr) /= dat_i then
-- report LF & " #### check NOT OK #### Value retrieved from memory DAT_I::::" & integer'image(to_integer(unsigned(dat_i))) &
-- "in address " & integer'image(adr) &
-- " of the Consumed variable does not match the corresponding one sent from FIP by the BA" & LF
-- severity warning;
-- errct_trig <= '1';
--end if;
if adr = 0 then
report " closing file!!!";
file_close(data_file_tmp1);
end if;
elsif var_id = 2 then
if in_broadcast(adr) /= dat_i then
report " #### check NOT OK #### Value retrieved from memory in address " &
......
syn/spec/spec_masterfip.xise
View file @ 30aa75bc
This diff is collapsed.
syn/spec/tb_masterFIP.fdo
View file @ 30aa75bc
######################################################################
##
## Filename: tb_masterFIP.fdo
## Created on: Fri Jul 22 18:44:57 W. Europe Daylight Time 2016
## Created on: Tue Oct 04 14:18:34 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Behavioral Simulation
##
......@@ -60,8 +60,6 @@ vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
vlog "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_package.vhd"
vlib nanoFIP_lib
......@@ -88,7 +86,6 @@ vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/textutil.vhd"
vcom -explicit -93 "../../sim/spec/testbench/encounter.vhd"
vcom -explicit -93 "../../rtl/serialIdTempInt.vhd"
vcom -explicit -93 "../../rtl/masterfip_tx.vhd"
vcom -explicit -93 "../../rtl/masterfip_rx.vhd"
vcom -explicit -93 "../../rtl/incr_counter.vhd"
......@@ -105,7 +102,6 @@ vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
......@@ -143,7 +139,6 @@ vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router1.vhd"
vcom -explicit -93 "../../rtl/fmc_masterFIP_core.vhd"
vcom -explicit -93 "../../rtl/carrier_info.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../../top/spec/spec_masterFIP.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_interface.vhd"
......@@ -153,11 +148,10 @@ vcom -explicit -93 "../../sim/spec/testbench/gnum_model/gn412x_bfm.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router.vhd"
vcom -explicit -93 "../../sim/spec/testbench/board_settings.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_masterFIP.vhd"
vlog "C:/EDA/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ps -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work work.tb_masterFIP glbl
vsim -voptargs="+acc" -t 1ps -lib work work.tb_masterFIP
#
# Source the wave do file
#
......
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