testbench: moved the VHDL legacy TB to testbench/legacy

22a3bb5b · Tomasz Wlostowski · 74004b07 · 22a3bb5b · 22a3bb5b · 22a3bb5b
Commit 22a3bb5b authored Feb 09, 2018 by Tomasz Wlostowski
52 changed files
--- a/sim/spec/data_vectors/WFIP_communication_config.txt
+++ b/sim/spec/data_vectors/WFIP_communication_config.txt
--- a/sim/spec/data_vectors/board_settings_config.txt
+++ b/sim/spec/data_vectors/board_settings_config.txt
--- a/sim/spec/data_vectors/errors_config.txt
+++ b/sim/spec/data_vectors/errors_config.txt
--- a/sim/spec/data_vectors/masterFIP_test.vec
+++ b/sim/spec/data_vectors/masterFIP_test.vec
--- a/sim/spec/data_vectors/user_logic_config.txt
+++ b/sim/spec/data_vectors/user_logic_config.txt
--- a/sim/spec/data_vectors/user_sequence.txt
+++ b/sim/spec/data_vectors/user_sequence.txt
--- a/sim/spec/tb_masterfip.do
+++ b/sim/spec/tb_masterfip.do
--- a/sim/spec/testbench/board_settings.vhd
+++ b/sim/spec/testbench/board_settings.vhd
--- a/sim/spec/testbench/encounter.vhd
+++ b/sim/spec/testbench/encounter.vhd
--- a/sim/spec/testbench/gnum_model/cmd_router.vhd
+++ b/sim/spec/testbench/gnum_model/cmd_router.vhd
--- a/sim/spec/testbench/gnum_model/cmd_router1.vhd
+++ b/sim/spec/testbench/gnum_model/cmd_router1.vhd
--- a/sim/spec/testbench/gnum_model/gn412x_bfm.vhd
+++ b/sim/spec/testbench/gnum_model/gn412x_bfm.vhd
--- a/sim/spec/testbench/gnum_model/mem_model.vhd
+++ b/sim/spec/testbench/gnum_model/mem_model.vhd
--- a/sim/spec/testbench/gnum_model/textutil.vhd
+++ b/sim/spec/testbench/gnum_model/textutil.vhd
--- a/sim/spec/testbench/gnum_model/util.vhd
+++ b/sim/spec/testbench/gnum_model/util.vhd
--- a/sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd
--- a/sim/spec/testbench/nanoFIP_lib/nanofip.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/nanofip.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_cons_outcome.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_cons_outcome.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_consumption.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_consumption.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_crc.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_crc.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_decr_counter.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_decr_counter.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_engine_control.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_engine_control.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_fd_receiver.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_fd_receiver.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_fd_transmitter.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_fd_transmitter.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_jtag_controller.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_jtag_controller.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_model_constr_decoder.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_model_constr_decoder.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_package.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_package.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_production.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_production.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd
--- a/sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd
+++ b/sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd
--- a/sim/spec/testbench/slone_interface.vhd
+++ b/sim/spec/testbench/slone_interface.vhd
--- a/sim/spec/testbench/slone_monitor.vhd
+++ b/sim/spec/testbench/slone_monitor.vhd
--- a/sim/spec/testbench/tb_masterFIP.vhd
+++ b/sim/spec/testbench/tb_masterFIP.vhd
--- a/sim/spec/testbench/tb_package.vhd
+++ b/sim/spec/testbench/tb_package.vhd
--- a/sim/spec/testbench/user_access_monitor.vhd
+++ b/sim/spec/testbench/user_access_monitor.vhd
--- a/sim/spec/testbench/user_config.vhd
+++ b/sim/spec/testbench/user_config.vhd
--- a/sim/spec/testbench/user_interface.vhd
+++ b/sim/spec/testbench/user_interface.vhd
--- a/sim/spec/testbench/user_sequencer.vhd
+++ b/sim/spec/testbench/user_sequencer.vhd
--- a/sim/spec/testbench/wishbone_interface.vhd
+++ b/sim/spec/testbench/wishbone_interface.vhd
--- a/sim/spec/testbench/wishbone_monitor.vhd
+++ b/sim/spec/testbench/wishbone_monitor.vhd