Commit 22985393 authored by Evangelia Gousiou's avatar Evangelia Gousiou

switched general-cores and wr-cores to branched with solderpad lic

parent 2105a515
general-cores @ 417e297b
Subproject commit 8e7e01ef56a4af08f29fbe86f0166edd30ab903d
Subproject commit 417e297b228512aa55b0432178ada39e707a2ae5
wr-cores @ 39a5a6e6
Subproject commit d4b42139d3cf88ebbc3bb78eb718db9f5dcce305
Subproject commit 39a5a6e6953725b62b4abe946d0c814b808110b6
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Wed May 30 12:23:54 2018
PCBE13457:: Wed May 30 14:49:34 2018
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_urv_map.ncd
spec_masterfip_mt_urv.ncd spec_masterfip_mt_urv.pcf
......@@ -275,7 +275,7 @@ WARNING:Par:288 - The signal cmp_mock_turtle_urv/gen_cpus[1].U_CPU_Block/U_TheCo
Starting Router
Phase 1 : 93327 unrouted; REAL time: 13 secs
Phase 1 : 93327 unrouted; REAL time: 14 secs
Phase 2 : 85222 unrouted; REAL time: 16 secs
......@@ -285,19 +285,19 @@ Phase 4 : 37511 unrouted; (Par is working to improve performance) REAL tim
Updating file: spec_masterfip_mt_urv.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 53 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 49 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 53 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 49 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 53 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 49 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 53 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 49 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 55 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 51 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 6 mins
Total REAL time to Router completion: 6 mins
Total CPU time to Router completion: 6 mins 6 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 5 mins 56 secs
Total REAL time to Router completion: 5 mins 56 secs
Total CPU time to Router completion: 6 mins 2 secs
Partition Implementation Status
-------------------------------
......@@ -339,8 +339,8 @@ All signals are completely routed.
WARNING:Par:283 - There are 76 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 6 mins 6 secs
Total CPU time to PAR completion: 6 mins 12 secs
Total REAL time to PAR completion: 6 mins 2 secs
Total CPU time to PAR completion: 6 mins 8 secs
Peak Memory Usage: 779 MB
......
......@@ -503,7 +503,7 @@ Back to vhdl to continue elaboration
Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.
Elaborating entity <generic_dpram_split> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_split.vhd" Line 132: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_split.vhd" Line 127: Comparison between arrays of unequal length always returns FALSE.
Elaborating entity <mt_cpu_lr_wb_slave> (architecture <syn>) from library <work>.
......@@ -556,9 +556,9 @@ Elaborating entity <inferred_sync_fifo> (architecture <syn>) with generics from
Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.
Elaborating entity <generic_dpram_sameclock> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_sameclock.vhd" Line 90: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_sameclock.vhd" Line 168: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_sameclock.vhd" Line 200: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_sameclock.vhd" Line 102: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_sameclock.vhd" Line 180: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_sameclock.vhd" Line 212: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:634 - "C:\masterFIP\urv\masterfip-gw\ip_cores\mockturtle\hdl\rtl\cpu\mt_cpu_cb.vhd" Line 107: Net <local_regs_in_rmq_stat_out_i[7]> does not have a driver.
WARNING:HDLCompiler:746 - "C:\masterFIP\urv\masterfip-gw\ip_cores\mockturtle\hdl\rtl\cpu\mt_cpu_cb.vhd" Line 59: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\masterFIP\urv\masterfip-gw\ip_cores\mockturtle\hdl\rtl\cpu\mt_cpu_cb.vhd" Line 60: Range is empty (null range)
......@@ -578,7 +578,7 @@ Back to vhdl to continue elaboration
Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.
Elaborating entity <generic_dpram_split> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_split.vhd" Line 132: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "C:\masterFIP\urv\masterfip-gw\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_split.vhd" Line 127: Comparison between arrays of unequal length always returns FALSE.
Elaborating entity <mt_mqueue_host> (architecture <arch>) with generics from library <work>.
......@@ -14780,12 +14780,12 @@ cmp_sys_clk_pll/CLKOUT0 | 9.687| | | |
=========================================================================
Total REAL time to Xst completion: 186.00 secs
Total CPU time to Xst completion: 185.76 secs
Total REAL time to Xst completion: 182.00 secs
Total CPU time to Xst completion: 181.88 secs
-->
Total memory usage is 572592 kilobytes
Total memory usage is 573232 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 6589 ( 0 filtered)
......@@ -238,7 +238,7 @@ fd_rxd_i |tp1_o | 5.057|
---------------+---------------+---------+
Analysis completed Wed May 30 12:30:23 2018
Analysis completed Wed May 30 14:55:59 2018
--------------------------------------------------------------------------------
Trace Settings:
......
......@@ -1501,10 +1501,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="281"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_regs.h" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="282"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="283"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed May 30 12:07:31 2018
Mapped Date : Wed May 30 14:33:19 2018
Design Summary
--------------
......@@ -107,9 +107,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 5.79
Peak Memory Usage: 832 MB
Total REAL time to MAP completion: 16 mins 20 secs
Total CPU time to MAP completion (all processors): 21 mins 10 secs
Peak Memory Usage: 833 MB
Total REAL time to MAP completion: 16 mins 12 secs
Total CPU time to MAP completion (all processors): 21 mins
Table of Contents
-----------------
......
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