Commit 1d193d0d authored by kblantos's avatar kblantos

SVA added in TB

parent 85239351
This diff is collapsed.
vsim -voptargs="-O5 +notimingchecks +acc" -classdebug -L unisim -L XilinxCoreLib -t 1ps -nopsl -quiet work.main
vsim -voptargs="-O5 +notimingchecks +acc" -classdebug -sv_seed random -L unisim -L XilinxCoreLib -t 1ps -nopsl -quiet work.main
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
......@@ -2,7 +2,19 @@ onerror {resume}
quietly WaveActivateNextPane {} 0
# Main Testbench
add wave -noupdate /main/mosi_data
add wave -noupdate -expand -group TESTBENCH /main/mosi_data
add wave -noupdate -expand -group TESTBENCH /main/miso_data
add wave -noupdate -expand -group TESTBENCH /main/test_miso_data
add wave -noupdate -expand -group TESTBENCH /main/negedge_cnt
add wave -noupdate -expand -group TESTBENCH /main/posedge_cnt
add wave -noupdate -expand -group TESTBENCH /main/q_mosi_data
add wave -noupdate -expand -group TESTBENCH /main/q_miso_data
add wave -noupdate -expand -group TESTBENCH /main/operation
add wave -noupdate -expand -group TESTBENCH /main/data_len
add wave -noupdate -expand -group TESTBENCH /main/rmq_id
add wave -noupdate -expand -group TESTBENCH /main/basic_info
add wave -noupdate -expand -group TESTBENCH /main/cnt
# ERTEC
add wave -noupdate -expand -group ERTEC -color Orange /main/DUT/ertec_spi_clk_i
......
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