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MasterFIP - Gateware
Commit 16499777 authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎
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rtl/Manifest.py
View file @ 16499777
......@@ -8,8 +8,6 @@ files = [
"masterfip_wbgen2_csr.vhd",
"masterfip_wbgen2_pkg.vhd",
"wf_package.vhd",
"spi_slave.vhd",
"mt_profip_translator.vhd",
"spi_rmq_bridge.vhd"
]
rtl/rmq_stream_fifo.vhd 0 → 100644
View file @ 16499777
--============================================================================--
--! @file rmq_stream_fifo.vhd
--! @author Alen Arias Vazquez <alen.arias.vazquez@cern.ch>
--! @company CERN
--! @date 2023-03-01
--! @brief Fifo encapsulation of RMQ frames
--============================================================================--
--============================================================================--
-- Libraries & Packages --
--============================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mt_mqueue_pkg.all;
use work.gencores_pkg.all;
--============================================================================--
-- Entity declaration for rmq_stream_fifo --
--============================================================================--
entity rmq_stream_fifo is
generic (
g_DATA_WIDTH : natural;
g_CDC_ENABLE : natural range 0 to 1;
g_FIFO_DEPTH : natural := 128;
g_show_ahead : boolean := true
);
port (
rst_n_i : in std_logic; --! FPGA reset
--! RX
rmq_src_clk_i : in std_logic;
rmq_src_i : in t_mt_stream_source_in; --! (ready, pkt_ready)
rmq_src_o : out t_mt_stream_source_out; --! (data, hdr, valid, last, error)
rmq_src_config_i : in t_mt_stream_config_out; --! (adr, dat, we)
rmq_src_config_o : out t_mt_stream_config_in; --! (dat)
--! TX
rmq_snk_clk_i : in std_logic;
rmq_snk_i : in t_mt_stream_sink_in; --! (data, hdr, valid, last, error)
rmq_snk_o : out t_mt_stream_sink_out; --! (ready, pkt_ready)
rmq_snk_config_i : in t_mt_stream_config_out; --! (adr, dat, we)
rmq_snk_config_o : out t_mt_stream_config_in --! (dat)
);
end entity rmq_stream_fifo;
--============================================================================--
-- Architecture declaration --
--============================================================================--
architecture struct of rmq_stream_fifo is
--! Data encapsulation
signal s_fifo_input : std_logic_vector(g_DATA_WIDTH+2 downto 0);
signal s_fifo_output : std_logic_vector(g_DATA_WIDTH+2 downto 0);
--! Write enable
signal s_input_full : std_logic;
signal s_write_enable : std_logic;
--! Read enable
signal s_output_empty : std_logic;
signal s_read_enable : std_logic;
--------------------------------------------------------------------------------
-- Architecture Begin
--------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
--! Unused
rmq_src_config_o.dat <= (others => '0');
rmq_snk_config_o.dat <= (others => '0');
----------------------------------------------------------------------------
CDC_check: assert g_CDC_ENABLE = 0
report "The port rmq_snk_clk_i is ignored" severity note;
s_fifo_input <= rmq_snk_i.hdr & rmq_snk_i.last & rmq_snk_i.error & rmq_snk_i.data;
s_write_enable <= not(s_input_full) and rmq_snk_i.valid;
rmq_snk_o.ready <= not (s_input_full);
rmq_snk_o.pkt_ready <= not (s_input_full);
gen_CDC_false: if g_CDC_ENABLE = 0 generate
cmp_fifo: entity work.inferred_sync_fifo
generic map (
g_data_width => g_DATA_WIDTH+3,
g_size => g_FIFO_DEPTH,
g_show_ahead => g_show_ahead,
g_show_ahead_legacy_mode => true,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => false,
g_register_flag_outputs => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
port map(
rst_n_i => rst_n_i,
clk_i => rmq_src_clk_i,
d_i => s_fifo_input,
we_i => s_write_enable,
full_o => s_input_full,
q_o => s_fifo_output,
empty_o => s_output_empty,
rd_i => s_read_enable,
almost_empty_o => open,
almost_full_o => open,
count_o => open
);
end generate gen_CDC_false;
gen_CDC_true: if g_CDC_ENABLE = 1 generate
cmp_fifo: entity work.inferred_async_fifo
generic map (
g_data_width => g_DATA_WIDTH+3,
g_size => g_FIFO_DEPTH,
g_show_ahead => true,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_full => true,
g_with_wr_empty => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => false,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
port map (
rst_n_i => rst_n_i,
-- write port
clk_wr_i => rmq_snk_clk_i,
d_i => s_fifo_input,
we_i => s_write_enable,
wr_full_o => s_input_full,
wr_empty_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => open,
-- read port
clk_rd_i => rmq_src_clk_i,
q_o => s_fifo_output,
rd_empty_o => s_output_empty,
rd_i => s_read_enable,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open
);
end generate gen_CDC_true;
rmq_src_o.data <= s_fifo_output(g_DATA_WIDTH-1 downto 0);
rmq_src_o.hdr <= s_fifo_output(g_DATA_WIDTH+2);
rmq_src_o.last <= s_fifo_output(g_DATA_WIDTH+1);
rmq_src_o.error <= s_fifo_output(g_DATA_WIDTH);
rmq_src_o.valid <= not (s_output_empty);
s_read_enable <= rmq_src_i.ready and not(s_output_empty);
end architecture struct;
--============================================================================--
-- End Architecture --
--============================================================================--
testbench/cocotb/test/tb_rmq_stream_fifo/Makefile 0 → 100644
View file @ 16499777
# List of vhdl srcs
SRC_VHDL=rmq_stream_fifo.vhd
VHDL_SOURCES:=$(addprefix $(PWD)/../../../../rtl/,$(SRC_VHDL))
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/common/gc_sync.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
VHDL_SOURCES+=../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
VHDL_SOURCES+=../../../../ip_cores/mockturtle/hdl/rtl/mqueue/mt_mqueue_pkg.vhd
# TOPLEVEL is the top level design and module is the python test
TOPLEVEL:=rmq_stream_fifo
MODULE:=tb_rmq_stream_fifo
RTL_LIBRARY?=work
# Define variables
g_DATA_WIDTH?=32
g_CDC_ENABLE?=1
g_FIFO_DEPTH?=64
g_show_ahead?=true
SIM_ARGS=-voptargs=+acc=rn
SIM_ARGS+="-t ps"
# Generics for GHDL
SIM_ARGS+=-gg_DATA_WIDTH=${g_DATA_WIDTH}
SIM_ARGS+=-gg_CDC_ENABLE=${g_CDC_ENABLE}
SIM_ARGS+=-gg_FIFO_DEPTH=${g_FIFO_DEPTH}
SIM_ARGS+=-gg_show_ahead=${g_show_ahead}
VCOM_ARGS +=-autoorder -2008
SCRIPT_FILE=wave.do
# Target Simulator
SIM=questa
# PYHTON PATH to get python models
export PYTHONPATH:=$(PWD)/../models/:$(PYTHONPATH)
# Include common rules
include ../Makefile.config
testbench/cocotb/test/tb_rmq_stream_fifo/wave.do 0 → 100644
View file @ 16499777
# ##############################################################################
#
#
#
# ##############################################################################
onerror {resume}
quietly WaveActivateNextPane {} 0
#SNK
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rst_n_i
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rmq_src_clk_i
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rmq_snk_i.data
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rmq_snk_i.hdr
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rmq_snk_i.valid
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rmq_snk_i.last
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rmq_snk_i.error
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rmq_snk_o.ready
add wave -noupdate -expand -group SNK -color Orange /rmq_stream_fifo/rmq_snk_o.pkt_ready
# FIFO
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/rst_n_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/clk_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/d_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/we_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/full_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/q_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/empty_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/rd_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/almost_empty_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/almost_full_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_false/cmp_fifo/count_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/rst_n_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/clk_wr_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/d_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/we_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/wr_full_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/clk_rd_i
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/q_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/rd_empty_o
add wave -noupdate -expand -group FIFO -color White /rmq_stream_fifo/gen_CDC_true/cmp_fifo/rd_i
#SRC
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rst_n_i
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rmq_src_clk_i
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rmq_src_o.data
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rmq_src_o.hdr
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rmq_src_o.valid
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rmq_src_o.last
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rmq_src_o.error
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rmq_src_i.ready
add wave -noupdate -expand -group SRC -color GReen /rmq_stream_fifo/rmq_src_i.pkt_ready
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {5542152000 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 568
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {5541518608 ps} {5575594505 ps}
testbench/cocotb/test/tb_spi_rmq_bridge/tb_spi_rmq_bridge.py
View file @ 16499777
"""
Test SPI SLAVE
Test SPI RMQ BRIDGE
"""
import cocotb
......
top/svec/svec_masterfip_mt_urv.ucf
View file @ 16499777
......@@ -7,7 +7,7 @@
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
......@@ -16,7 +16,7 @@ NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
NET "ertec_spi_clk_i" LOC = "AC15";
NET "ertec_spi_clk_i" TIG;
NET "ertec_spi_clk_i" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "ertec_spi_clk_i" CLOCK_DEDICATED_ROUTE = FALSE;
NET "ertec_spi_clk_i" IOSTANDARD = "LVCMOS25";
NET "ertec_spi_cs_n_i" LOC = "AB19";
......@@ -62,10 +62,10 @@ NET "ertec_spi_miso_o" IOSTANDARD = "LVCMOS25";
# BANK 4 P2V5: SPEC LEDs
#----------------------------------------
NET "LED_RED_O" LOC = "D5";
NET "LED_RED_O" LOC = "D5";
NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = "E5";
NET "LED_GREEN_O" LOC = "E5";
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
......@@ -93,13 +93,13 @@ NET "ertec_gpio_18_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0
NET "fmc_onewire_b" LOC = "K11";
NET "fmc_onewire_b" LOC = "K11";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = "J12";
NET "led_tx_err_n_o" LOC = "J12";
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = "H12";
NET "led_tx_act_n_o" LOC = "H12";
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = "H11";
......@@ -174,3 +174,6 @@ NET "ertec_uart_rx_o" LOC = "AF23";
NET "ertec_uart_rx_o" IOSTANDARD = "LVCMOS25";
#PIN "cmp_mt_profip_translator/cmp_mosi_async_fifo/empty_int_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
TIMESPEC "TS_exception_cdc"= FROM "cmp_spi_rmq_bridge/clk_i" TO "cmp_spi_rmq_bridge/spi_sample_clk_i" TIG;
TIMESPEC "TS_exception_cdc_2"= FROM "cmp_spi_rmq_bridge/spi_sample_clk_i" TO "cmp_spi_rmq_bridge/clk_i" TIG;
#TIMESPEC "TS_exception666_3"= FROM "cmp_spi_rmq_bridge/spi_sample_clk_i/s_tx_reg_31" TO "cmp_spi_rmq_bridge/spi_miso_o" 15 ns DATAPATHONLY;
top/svec/svec_masterfip_mt_urv.vhd
View file @ 16499777
......@@ -475,12 +475,12 @@ begin
g_data_width => 32,
g_cpol => 0,
g_cpha => 1,
g_CDC_ENABLE => 0
g_CDC_ENABLE => 1
)
port map (
rst_n_i => local_reset_n,
clk_i => clk_62m5_sys,
rst_n_i => local_reset_n,
-- clk_ref_i => clk_125m_sys,
spi_sample_clk_i => clk_125m_sys,
rmq_src_i => rmq_src_in,
rmq_src_o => rmq_src_out,
rmq_src_config_i => rmq_snk_cfg_out,
......
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