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MasterFIP - Gateware
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Projects
MasterFIP - Gateware
Commits
03b4e543
Commit
03b4e543
authored
Mar 31, 2023
by
Alén Arias Vázquez
😎
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test
parent
8fc08782
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2 changed files
with
2 additions
and
6 deletions
+2
-6
.gitlab-ci.yml
.gitlab-ci.yml
+0
-6
spec_masterfip_mt.vhd
top/spec/spec_masterfip_mt.vhd
+2
-0
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.gitlab-ci.yml
View file @
03b4e543
...
...
@@ -48,12 +48,6 @@ gateware_spec:
rules
:
-
!reference
[
.default_rules
,
rules
]
-
if
:
$CI_PIPELINE_SOURCE == "merge_request_event"
changes
:
-
"
rtl/*.{vhd,v,sv}"
-
"
top/spec/*.{vhd,v,sv,ucf}"
-
"
syn/spec/Makefile"
-
"
syn/spec/*.{tcl,sh}"
-
"
ip_cores/**/*.{vhd,v,sv}"
-
if
:
$CI_COMMIT_REF_NAME =~ /^\d+-/
changes
:
-
"
rtl/*.{vhd,v,sv}"
...
...
top/spec/spec_masterfip_mt.vhd
View file @
03b4e543
...
...
@@ -326,6 +326,8 @@ architecture rtl of spec_masterfip_mt is
constant
C_SLAVE_ADDR
:
t_wishbone_address_array
(
0
downto
0
):
=
(
0
=>
x"00000000"
);
constant
C_SLAVE_MASK
:
t_wishbone_address_array
(
0
downto
0
):
=
(
0
=>
x"00000000"
);
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
...
...
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