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...@@ -7,9 +7,10 @@ channels each with a fixed threshold discriminator and a slow shaper + ...@@ -7,9 +7,10 @@ channels each with a fixed threshold discriminator and a slow shaper +
sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet
(firmware supplied supports IPBus). Multiple boards can be plugged (firmware supplied supports IPBus). Multiple boards can be plugged
together to increase the channel count. Clocking circuitry compatible together to increase the channel count. Clocking circuitry compatible
with the White Rabbit implementation of PTP. with the White Rabbit implementation of
PTP.
PICT0015.JPG [![](/uploads/47d737deae7c9d6edc8b8e80d4910566/Maroc_topside_s.jpg)](Maroc\_topside\_l.jpg)
*Single MAROC board, with 1000Base-T SFP *Single MAROC board, with 1000Base-T SFP
inserted.** inserted.**
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