| ... | @@ -11,100 +11,25 @@ with the White Rabbit implementation of |
... | @@ -11,100 +11,25 @@ with the White Rabbit implementation of |
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PTP.
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PTP.
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[](Maroc\_topside\_l.jpg)
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[](Maroc\_topside\_l.jpg)
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*Single MAROC board, with 1000Base-T SFP
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*Single MAROC board, with 1000Base-T SFP inserted.**
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inserted.**
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[](/project/white-rabbit/uploads/0eeb5b430351eca8a4e76a5af3892c2c/svectop_l.png)
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*SVEC V1 production board** - [block
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diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df19c/Block.png)
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## Main Features
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## Main Features
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- VME64x interface
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- MAROC3 ASIC with 64 channels. Adjustable gain amplifiers. Adjustable
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- Two Low-Pin Count FMC slots
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shaping time. 12 bit ADC
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- Vadj fixed to 2.5V
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- Xilinx Spartan-3 FPGA
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- No dedicated clock signals from Carrier to FMC (as only
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- Read out using IPBus over Gigabit Ethernet.
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available on HPC pins and use LPC)
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- Single +12V supply
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- FMC connectivity: all 34 differential pairs connected, 1 GTP
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\---
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transceiver with clock, 2 clock pairs, JTAG
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- Xilinx FPGAs
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- Application FPGA: Spartan-6 XC6SLX150T-3FGG900C
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- Direct connection to all resources such as VME64x, memories
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and FMC connectors
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- System FPGA: Spartan-6 XC6SLX9-2FTG256C
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- Provides VME bootloader, early oscillator/PLL config
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- Configuration Flash memory for both Main FPGA and
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Application FPGA configuration
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- FPGA configuration
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- From SPI flash or via VME
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- Clocking resources
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- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
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MHz (Silicon Labs Si570, freely usable)
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- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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- 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed
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configuration, Fout=125 MHz, used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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- On-board memories
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- 2x 256 MByte (2 Gbit) DDR3 (16-bit bus, MT41J128M16JT-125)
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- 1x 128 Mbit SPI flash for FPGA firmware storage (M25P128-VME6GB)
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- 64kbit EEPROM connected for storing application parameters
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(24AA64T-I/MC)
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- 1x I2C configuration EEPROM (24LC64)
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- Miscellaneous
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- On-board thermometer IC (DS18B20U+)
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- Unique 64-bit identifier (DS18B20U+)
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- Front panel
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- 1x SFP port ([White
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Rabbit](https://www.ohwr.org/project/white-rabbit/wikis/)
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compatible)
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- 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
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- 2x mini displayPort connectors for high-speed serial GTP links
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(not for video)
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- 8x Programmable LED
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- Reset push button
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- Internal connectors
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- VME P2 connector provides access to a Rear Transition Module
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(compatible to
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[VFC](https://www.ohwr.org/project/fmc-vme-carrier/wiki))
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- 40 user defined single ended (Vcco=2.5V) signals (or 20 LVDS
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pairs) connected to the Application FPGA
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- 2x 125 MHz LVDS clocks provided to the RTM
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- Xilinx-style JTAG connector
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- Internal mini USB 2.0 High Speed connector for stand-alone
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applications (CP2103)
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- Optional features, check with vendor
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- Internal 2 x SATA connector for stand-alone PCI Express
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connectivity (clock + data)
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- Internal 4 x UFL connectors with low-jitter clock for FMC cards
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- Internal additional USB 2.0 on 4-pin header (FT2232HL)
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- Battery for secure storage of FPGA configuration data
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- Stand-alone features
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- External supply connector (3.3V, 5V) on internal SATA
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connector
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- PCIe interface on internal SATA connector
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- 10-layer PCB
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-----
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## Project information
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## Project information
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- Official production documentation:
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- Circuit schematic capture and PCB layout (Using Cadence Allegro
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[EDA-02530](http://edms.cern.ch/nav/eda-02530)
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tools ) in Git repository:
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- [Hardware
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- [Circuit Schematic](circuit_schematic)
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manual](http://www.janztec.com/fileadmin/downloads/manuals/manual_svec_hardware.pdf)
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(Janz Tec)
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- [Block diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df19c/Block.png)
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- [CERN specific information](CERN)
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- [Users](Users)
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- [Users](Users)
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- [Software](Software)
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- [Software](Software)
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- [Standard Gateware](https://www.ohwr.org/project/svec/wikis/documents) (and
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- [Firmware](Firmware)
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[how to use it](https://www.ohwr.org/project/svec/wikis/Documents/SVEC-Gateware-Manual))
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- [Frequently Asked Questions](FAQ)
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-----
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-----
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| ... | @@ -112,26 +37,15 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
... | @@ -112,26 +37,15 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
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*Latest:**
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*Latest:**
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- Hardware: v3.0 -
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- Hardware v1.0 - [point to artwork](http://point) to artwork
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[EDA-02530-V3-0](https://edms.cern.ch/nav/EDA-02530-V3-0)
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- Firmware v1.0 - - [point-to-firmware](point-to-firmware)
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- Gateware: v3.0 - [Gateware release 3.0](Gateware-Release-3-0)
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- Linux driver: see [Software support for
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SVEC](https://www.ohwr.org/project/svec-sw/wiki) Project
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*All Gateware releases:** See the [Releases](Releases) page.
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-----
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-----
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## Contacts
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## Contacts
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### Commercial producers
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- [David Cussans](mailto:David.Cussans@bristol.ac.uk) - University of
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Bristol
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- [SVEC - BO-FVM-SVEC0](http://www.janztec.com/en/vme64xsvec.html)
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[Janz Tec AG](http://www.janztec.com/en/), Germany
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### General question about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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-----
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-----
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| ... | @@ -144,91 +58,15 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
... | @@ -144,91 +58,15 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
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<td><b> Event </b></td>
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<td><b> Event </b></td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>01-07-2011</td>
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<td>01-07-2015</td>
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<td>First ideas for starting this simpler and cheaper version of the [FMC VME Carrier](https://www.ohwr.org/project/fmc-vme-carrier).</td>
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<td>Board available</td>
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</tr>
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<tr class="odd">
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<td>19-07-2011</td>
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<td>Main features specification written.</td>
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</tr>
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<tr class="even">
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<td>25-10-2011</td>
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<td>Order sent out to a company for the schematics design.</td>
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</tr>
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<tr class="odd">
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<td>02-05-2012</td>
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<td>V0 files created. Ordered 4 assembled boards.</td>
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</tr>
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<tr class="even">
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<td>05-06-2012</td>
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<td>V1: replace eSATA by microHDMI, remove front USB (space reasons).</td>
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</tr>
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<tr class="odd">
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<td>15-06-2012</td>
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<td>Four V0 boards received at CERN.</td>
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</tr>
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<tr class="even">
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<td>21-06-2012</td>
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<td>V0: VME works, bootloader works, White Rabbit works, FMC slots work (two Fine Delay cards operating correctly)</td>
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</tr>
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<tr class="odd">
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<td>04-09-2012</td>
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<td>V1 of design released. Ordered 9. Price Enquiry for production of 90 will follow soon.</td>
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</tr>
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<tr class="even">
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<td>24-10-2012</td>
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<td>Four V1 boards received.</td>
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</tr>
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<tr class="odd">
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<td>01-11-2012</td>
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<td>V2 design files released. <a href="https://www.ohwr.org/project/svec/versions/12">Minor corrections</a> on mechanics and one electrical issue.</td>
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</tr>
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<tr class="even">
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<td>05-11-2012</td>
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<td>90 boards ordered. 30 for delivery end January 2013, 60 for end March 2013.</td>
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</tr>
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<tr class="odd">
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<td>08-02-2013</td>
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<td>30 V1-0 boards received at CERN.</td>
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</tr>
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<tr class="even">
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<td>17-07-2013</td>
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<td>10 V2-0 pre-series boards received.</td>
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</tr>
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<tr class="odd">
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<td>31-07-2013</td>
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<td>28 additional board ordered.</td>
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</tr>
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<tr class="even">
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<td>09-10-2013</td>
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<td>50 V2-0 series boards received.</td>
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</tr>
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<tr class="odd">
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<td>08-11-2013</td>
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<td>28 V2-0 series boards received (in total 118 received).</td>
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</tr>
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<tr class="even">
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<td>05-12-2013</td>
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<td><a href="http://www.janztec.com/fileadmin/downloads/manuals/manual_svec_hardware.pdf">Hardware manual</a> written by Janz Tec.</td>
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</tr>
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<tr class="odd">
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<td>02-04-2014</td>
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<td><a href="Gateware-Release-2-0">Release 2.0</a> of the SVEC standard gateware (bootloader & golden) is available</td>
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</tr>
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<tr class="even">
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<td>20-10-2014</td>
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<td>V3-0 released. Changes can be seen in [Roadmap](https://www.ohwr.org/project/svec/roadmap?completed=1)</td>
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</tr>
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<tr class="odd">
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<td>26-11-2014</td>
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<td><a href="Gateware-Release-3-0">Release 3.0</a> of the SVEC bootloader is available</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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-----
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-----
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17 March 2015
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24 April 2016
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| ... | | ... | |
