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![](/uploads/96b634b480d87934177bf702c5b0d1b8/whole_system_half.png)
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In the library, we are providing right now components for estimating the
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optical flow (based on energy and phase), stereo disparity (based on
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energy and phase), and local energy, orientation, and
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phase.
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![](/uploads/2f760813454591b5245eba013657e2ad/output_features.png)
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The general rule for the implementation of the different modules is
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based on a modular design of a fine-grain pipelined and superscalar
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datapath to reach high performance at low working clock frequencies. The
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The design strategy requires the accurate definition of very deep
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pipelined datapaths with concurrent accesses to external memory banks.
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In order to facilitate the management of concurrent external memory
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accesses, we have used a customized memory control
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unit.
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![](/uploads/2f760813454591b5245eba013657e2ad/output_features.png)
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accesses, we have used a customized memory control unit.
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This fine grain pipeline strategy adopted for the core increases the
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maximum clock frequency by reducing the largest path delay between the
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real-time performance. This means that once the pipeline is filled, the
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circuit is able to process one pixel per clock cycle.
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More details of the different modules and the strategy can be found in
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the respective subprojects, the papers in the documentation, and the
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repository.
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## Library components
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\- [Optical flow
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