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Hydra - a radiation-tolerant SoC
Commit f75d5e11 authored by Tristan Gingold's avatar Tristan Gingold
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hdl: reformatting

parent da511871
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Showing with 1235 additions and 1588 deletions
hdl/dpram_generic.vhd
View file @ f75d5e11
......@@ -9,11 +9,9 @@ use ieee.numeric_std.all;
entity dpram_generic is
generic (
g_addr_width : natural := 15;
g_data_width : natural := 42
);
port (
clk_i : in std_logic;
......@@ -38,17 +36,14 @@ entity dpram_generic is
qb_o : out std_logic_vector(g_data_width-1 downto 0);
valid_a_o : out std_logic;
valid_b_o : out std_logic
);
end dpram_generic;
architecture rtl of dpram_generic is
component RAM1K18
-- generic (MEMORYFILE:string := "");
port(A_DOUT : out std_logic_vector(17 downto 0);
-- generic (MEMORYFILE:string := "");
port (
A_DOUT : out std_logic_vector(17 downto 0);
B_DOUT : out std_logic_vector(17 downto 0);
BUSY : out std_logic;
A_CLK : in std_logic := 'U';
......@@ -85,7 +80,6 @@ architecture rtl of dpram_generic is
signal qa, qb, da, db : std_logic_vector (g_data_width downto 0);
signal addr_match : std_logic;
signal lock_a_req, lock_b_req : std_logic;
......@@ -95,18 +89,14 @@ architecture rtl of dpram_generic is
signal wea, web : std_logic_vector (39 downto 0);
signal qa_discard_32k, qb_discard_32k : std_logic_vector (17 downto 2);
signal qa_discard_64k, qb_discard_64k : std_logic_vector (17 downto 1);
signal rea, reb : std_logic;
signal wa_voted, wb_voted : std_logic;
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of rtl : architecture is "tmr";
signal wa_voted : std_logic;
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of rtl : architecture is "tmr";
begin
addr_match <= '1' when (aa_i (7 downto 2) = ab_i (7 downto 2)) else '0'; --to save LUTs, overhead
--is only 0.5% (random address)
da <= "0" & da_i;
......@@ -119,7 +109,6 @@ begin
process (lock_b_grant, lock_a_grant, addr_match, ra_i, rb_i, wa_voted, wb_i)
begin
if (lock_b_grant = '1') then
valid_b_o <= '1';
else
......@@ -128,33 +117,26 @@ begin
if (lock_a_grant = '1') then
valid_a_o <= '1';
else
else
valid_a_o <= '0' when (((ra_i and wb_i) or lock_b_grant) and addr_match) else '1';
end if;
end process;
end if;
end process;
tmr_signals : for i in 0 to 39 generate
tmr_signals : for i in 0 to 39 generate
wea (i) <= ( (wa_i(1) and wa_i(2)) or (wa_i(1) and wa_i(3)) or (wa_i(2) and wa_i(3))) and valid_a_o;
-- "web" signal not TMRed (it requires a block TMR of the scrubber)
web (i) <= wb_i and valid_b_o;
end generate;
end generate;
lock_a_grant_o <= lock_a_grant;
lock_b_grant_o <= lock_b_grant;
lock_contention <= addr_match and lock_a_req_i and lock_b_req_i;
lock_a_req <= lock_a_req_i;
lock_b_req <= lock_b_req_i;
assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error grant" severity error;
assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error grant" severity error;
process (clk_i, rst_i)
begin
......@@ -165,7 +147,6 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
else
lock_a_grant_d <= lock_a_grant;
lock_b_grant_d <= lock_b_grant;
end if;
end if;
end process;
......@@ -174,7 +155,6 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
process (lock_contention, lock_a_req, lock_b_req, lock_a_grant_d, lock_b_grant_d)
begin
if (lock_contention = '0') then
lock_a_grant <= lock_a_req;
lock_b_grant <= lock_b_req;
......@@ -195,7 +175,6 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
lock_b_grant <= lock_b_grant_d;
end if;
end if;
end process;
......@@ -203,7 +182,7 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
gen_bram : for i in 1 to 5 generate
gen_byte : for k in 0 to 3 generate
sram_two_bit : RAM1K18
inst_sram_two_bit : RAM1K18
port map(
A_WIDTH => "001",
......@@ -244,24 +223,18 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
B_ADDR (0 downto 0) => "0",
B_ADDR (13 downto 1) => ab_i(14 downto 2),
A_BLK => (others => '1'),
B_BLK => (others => '1'),
A_DOUT (17 downto 2) => qa_discard_32k (17 downto 2),
A_DOUT (1 downto 0) => qa(8*(i-1)+2*k+1 downto 8*(i-1)+2*k),
b_DOUT (17 downto 2) => qb_discard_32k (17 downto 2),
B_DOUT (1 downto 0) => qb(8*(i-1)+2*k+1 downto 8*(i-1)+2*k)
);
end generate gen_byte;
end generate gen_bram;
sram_two_bit : RAM1K18
port map(
A_WIDTH => "001",
B_WIDTH => "001",
......@@ -308,20 +281,13 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
A_DOUT (1 downto 0) => qa(41 downto 40),
b_DOUT (17 downto 2) => qb_discard_32k(17 downto 2),
B_DOUT (1 downto 0) => qb(41 downto 40)
);
end generate gen_32k_daec;
gen_64k : if g_addr_width = 16 generate
gen_bram : for i in 1 to 5 generate
gen_byte : for k in 0 to 7 generate
sram_bit : RAM1K18
port map(
A_WIDTH => "000",
B_WIDTH => "000",
......@@ -361,7 +327,6 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
--B_ADDR (0 downto 0) => "0",
B_ADDR (13 downto 0) => ab_i(15 downto 2),
A_BLK => (others => '1'),
B_BLK => (others => '1'),
......@@ -369,13 +334,8 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
A_DOUT (0 downto 0) => qa(8*(i-1)+k downto 8*(i-1)+k),
b_DOUT (17 downto 1) => qb_discard_64k,
B_DOUT (0 downto 0) => qb(8*(i-1)+k downto 8*(i-1)+k)
);
end generate gen_byte;
end generate gen_bram;
end generate gen_64k;
end architecture;
\ No newline at end of file
end architecture;
hdl/ram_voter.vhd
View file @ f75d5e11
......@@ -26,7 +26,6 @@ entity ram_voter is
generic (
g_addr_width : natural := 15;
g_data_width : natural := 38
);
port (
da_vot_i : in t_voter_stdvector (open)(g_data_width-1 downto 0);
......@@ -41,34 +40,23 @@ entity ram_voter is
wa_o : out std_logic;
ra_o : out std_logic;
lock_a_req_o : out std_logic
);
end ram_voter;
architecture rtl of ram_voter is
begin
da : for i in da_o'range generate
da_o(i) <= (da_vot_i(1)(i) and da_vot_i(2)(i)) or (da_vot_i(2)(i) and da_vot_i(3)(i)) or (da_vot_i(1)(i) and da_vot_i(3)(i));
end generate;
aa : for i in aa_o'range generate
aa_o(i) <= (aa_vot_i(1)(i) and aa_vot_i(2)(i)) or (aa_vot_i(2)(i) and aa_vot_i(3)(i)) or (aa_vot_i(1)(i) and aa_vot_i(3)(i));
end generate;
wa_o <= (wa_vot_i(1) and wa_vot_i(2)) or (wa_vot_i(2) and wa_vot_i(3)) or (wa_vot_i(1) and wa_vot_i(3));
ra_o <= (ra_vot_i(1) and ra_vot_i(2)) or (ra_vot_i(2) and ra_vot_i(3)) or (ra_vot_i(1) and ra_vot_i(3));
lock_a_req_o <= (lock_a_req_vot_i(1) and lock_a_req_vot_i(2)) or (lock_a_req_vot_i(2) and lock_a_req_vot_i(3)) or (lock_a_req_vot_i(1) and lock_a_req_vot_i(3));
end architecture;
hdl/secded_ecc.vhd
View file @ f75d5e11
......@@ -165,7 +165,6 @@ architecture rtl of secded_ecc is
end f_ecc_errors;
function f_ecc_one_error (syndrome : std_logic_vector (6 downto 0)) return std_logic is
variable syndrome_bound_check : std_logic;
begin
if Is_x (syndrome (0)) then
return '0';
......
hdl/seu_counters.vhd
View file @ f75d5e11
......@@ -13,12 +13,8 @@ use work.wishbone_pkg.all;
--use smartfusion2.all;
use work.voter.all;
use work.wb_voter_pkg.all;
entity seu_counters is
port (
clk_i : in std_logic;
rst_i : in std_logic;
......@@ -34,16 +30,14 @@ entity seu_counters is
se_iram_o : out std_logic_vector (15 downto 0);
de_iram_o : out std_logic_vector (15 downto 0)
);
end entity seu_counters;
architecture rtl of seu_counters is
signal se_iram_counter,de_iram_counter,se_dram_counter,de_dram_counter : unsigned (15 downto 0);
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of rtl : architecture is "tmr";
attribute syn_radhardlevel of rtl : architecture is "tmr";
begin
......
hdl/urv_core_DTMR.vhd
View file @ f75d5e11
......@@ -187,12 +187,12 @@ end component;
signal im_addr, dm_addr, dram_addr : std_logic_vector(31 downto 0);
signal im_data, im_data_cpu, im_data_bank1, dram_data_in, dram_data_out : std_logic_vector(31 downto 0);
signal im_valid, im_valid_cpu, im_valid_bank1 : std_logic;
signal im_data, dram_data_in, dram_data_out : std_logic_vector(31 downto 0);
signal im_valid : std_logic;
signal dm_data_s, dm_data_l, dm_data_ram, dm_wb_rdata : std_logic_vector(31 downto 0);
signal dm_data_s, dm_data_l, dm_wb_rdata : std_logic_vector(31 downto 0);
signal dm_data_select, dram_bwe : std_logic_vector(3 downto 0);
signal dm_load, dm_store, dm_done, dm_ready, dram_we, dram_re : std_logic;
signal dm_load, dm_store, dram_we, dram_re : std_logic;
signal dram_done_r, dram_done_w : std_logic;
signal dm_is_wishbone, dm_cycle_in_progress, dm_load_done_wb, dm_store_done_wb : std_logic;
......
hdl/urv_soc.vhd
View file @ f75d5e11
This diff is collapsed.
hdl/urv_supervisor.vhd
View file @ f75d5e11
......@@ -13,7 +13,6 @@ use work.wishbone_pkg.all;
--use smartfusion2.all;
use work.voter.all;
use work.wb_voter_pkg.all;
......@@ -48,7 +47,6 @@ architecture rtl of urv_supervisor is
signal state_cpu_1, state_cpu_2, state_cpu_3 : std_logic;
signal state_cpu : std_logic_vector (3 downto 1);
signal release_cpu : std_logic;
type fsm_states is (boot, boot_cnt, voting, lock_step, fatal, fatal_2);
constant recovery_dunc : std_logic_vector (15 downto 0) := x"0000";
......
hdl/wb_envm.vhd
View file @ f75d5e11
......@@ -7,7 +7,6 @@ use work.wishbone_pkg.all;
entity wb_envm is
port (
clk_i : in std_logic;
rst_i : in std_logic;
......@@ -27,46 +26,45 @@ entity wb_envm is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
);
end entity wb_envm;
architecture rtl of wb_envm is
constant bootloader_addr : std_logic_vector (31 downto 0) := x"60012000"; -- (bits from 11 to 0 must be 0)
constant bootloader_size : integer := 256; -- words (max 256)
constant bootloader_addr : std_logic_vector (31 downto 0) := x"60012000"; -- (bits from 11 to 0 must be 0)
constant bootloader_size : integer := 256; -- words (max 256)
type fsm_apb_states is (idle, setup, accessing);
type fsm_envm_states is (idle, check_status, poll_bit, data);
type fsm_bootstrap_states is (cold_start, poll_bit, fetch_word, wait_apb, wait_wb, checksum, done);
type fsm_wb_master_states is (idle, wait_ack);
type fsm_apb_states is (idle, setup, accessing);
type fsm_envm_states is (idle, check_status, poll_bit, data);
type fsm_bootstrap_states is (cold_start, poll_bit, fetch_word, wait_apb, wait_wb, checksum, done);
type fsm_wb_master_states is (idle, wait_ack);
signal apb_fsm : fsm_apb_states := idle;
signal envm_fsm : fsm_envm_states := idle;
signal bootstrap_fsm : fsm_bootstrap_states := cold_start;
signal wb_fsm : fsm_wb_master_states := idle;
signal apb_fsm : fsm_apb_states := idle;
signal envm_fsm : fsm_envm_states := idle;
signal bootstrap_fsm : fsm_bootstrap_states := cold_start;
signal wb_fsm : fsm_wb_master_states := idle;
signal apb_addr, apb_addr_boot, apb_addr_wb, envm_addr, envm_data, apb_data, wb_data, wb_data_reg : std_logic_vector (31 downto 0);
signal apb_addr, apb_addr_boot, apb_addr_wb, envm_addr, envm_data, apb_data, wb_data, wb_data_reg : std_logic_vector (31 downto 0);
signal envm_read_req_p, apb_read_req, apb_read_req_boot, apb_read_req_wb, apb_read_ack : std_logic;
signal wb_write_req, wb_write_req_boot, wb_write_req_wb, wb_write_ack : std_logic;
signal wb_addr, wb_addr_boot, wb_addr_wb : std_logic_vector (16 downto 0);
signal envm_read_req_p, apb_read_req, apb_read_req_boot, apb_read_req_wb, apb_read_ack:std_logic;
signal wb_write_req, wb_write_req_boot, wb_write_req_wb, wb_write_ack : std_logic;
signal wb_addr, wb_addr_boot, wb_addr_wb : std_logic_vector (16 downto 0);
signal counter : unsigned (9 downto 0);
attribute syn_encoding : string;
attribute syn_encoding of bootstrap_fsm, wb_fsm, apb_fsm, envm_fsm : signal is "safe,onehot";
attribute syn_encoding : string;
attribute syn_encoding of bootstrap_fsm, wb_fsm, apb_fsm, envm_fsm : signal is "safe,onehot";
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of rtl : architecture is "tmr";
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of rtl : architecture is "tmr";
begin
apb_addr <= apb_addr_boot when (rst_cpu_o = '1') else apb_addr_wb;
apb_read_req <= apb_read_req_boot when (rst_cpu_o = '1') else apb_read_req_wb;
apb_addr <= apb_addr_boot when (rst_cpu_o = '1') else apb_addr_wb;
apb_read_req <= apb_read_req_boot when (rst_cpu_o = '1') else apb_read_req_wb;
process (clk_i)
begin
if rising_edge (clk_i) then
-- Start FSM: copy from NVM to RAM.
process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
rst_cpu_o <= '1';
bootstrap_fsm <= cold_start;
......@@ -74,6 +72,7 @@ if rising_edge (clk_i) then
else
case (bootstrap_fsm) is
when cold_start =>
-- Init
rst_cpu_o <= '1';
bootstrap_fsm <= poll_bit;
counter <= (others => '0');
......@@ -81,6 +80,7 @@ if rising_edge (clk_i) then
apb_addr_boot <= x"60080120";
apb_read_req_boot <= '1';
when poll_bit =>
-- Wait NVM ready
apb_read_req_boot <= '0';
if (apb_read_ack = '1') then
if (apb_data (0) = '1') then -- busy bit
......@@ -90,12 +90,14 @@ if rising_edge (clk_i) then
end if;
end if;
when fetch_word =>
-- Read a word from the NVM
apb_read_req_boot <= '1';
apb_addr_boot (31 downto 12) <= bootloader_addr (31 downto 12);
apb_addr_boot (11 downto 2) <= std_logic_vector(counter);
apb_addr_boot (1 downto 0) <= (others => '0');
bootstrap_fsm <= wait_apb;
when wait_apb =>
-- Wait NVM word
apb_read_req_boot <= '0';
if (apb_read_ack = '1') then
bootstrap_fsm <= wait_wb;
......@@ -104,6 +106,7 @@ if rising_edge (clk_i) then
wb_addr_boot (11 downto 2) <= std_logic_vector(counter);
end if;
when wait_wb =>
-- Write to RAM
wb_write_req_boot <= '0';
if (wb_write_ack = '1') then
if (counter >= to_unsigned(bootloader_size-4, counter'length)) then
......@@ -122,17 +125,18 @@ if rising_edge (clk_i) then
bootstrap_fsm <= done;
end case;
end if;
end if;
end process;
end if;
end process;
wb_addr <= wb_addr_boot when (rst_cpu_o = '1') else wb_addr_wb;
wb_write_req <= wb_write_req_boot when (rst_cpu_o = '1') else wb_write_req_wb;
wb_data <= apb_data when (rst_cpu_o = '1') else wb_data_reg;
wb_addr <= wb_addr_boot when (rst_cpu_o = '1') else wb_addr_wb;
wb_write_req <= wb_write_req_boot when (rst_cpu_o = '1') else wb_write_req_wb;
wb_data <= apb_data when (rst_cpu_o = '1') else wb_data_reg;
process (clk_i)
begin
if rising_edge (clk_i) then
-- WB fsm
process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
wb_fsm <= idle;
master_o.cyc <= '0';
......@@ -164,15 +168,14 @@ if rising_edge (clk_i) then
when others =>
wb_fsm <= idle;
end case;
end if;
end if;
end process;
end if;
end process;
process (clk_i)
begin
if rising_edge(clk_i) then
-- APB fsm
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
apb_fsm <= idle;
apb_psel_o <= '0';
......@@ -203,12 +206,12 @@ if rising_edge(clk_i) then
apb_fsm <= idle;
end case;
end if;
end if;
end process;
end if;
end process;
process (clk_i)
begin
if rising_edge (clk_i) then
process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
envm_fsm <= idle;
apb_read_req_wb <= '0';
......@@ -244,35 +247,41 @@ if rising_edge (clk_i) then
when others =>
envm_fsm <= idle;
end case;
end if;
end if;
end process;
end if;
end if;
end process;
process (clk_i)
begin
if rising_edge (clk_i) then
-- WB slave: decode accesses
process (clk_i)
begin
if rising_edge (clk_i) then
envm_read_req_p <= '0';
wb_write_req_wb <= '0';
slave_o.ack <= '0';
if (slave_i.stb = '1' and slave_i.cyc = '1' and slave_o.ack = '0') then
slave_o.ack <= '1';
if (slave_i.adr(4 downto 2) = "000") then
-- Status
slave_o.dat (31 downto 1) <= (others => '0');
slave_o.dat (0) <= '1' when envm_fsm /= idle else '0';
elsif (slave_i.adr (4 downto 2) = "001") then
-- Start NVM read access
slave_o.dat <= slave_i.dat;
if (slave_i.we = '1') then
envm_addr <= slave_i.dat;
envm_read_req_p <= '1';
end if;
elsif (slave_i.adr (4 downto 2) = "010") then
-- NVM data
slave_o.dat <= envm_data;
elsif (slave_i.adr (4 downto 2) = "100") then
-- ???
slave_o.dat <= slave_i.dat;
if (slave_i.we = '1') then
wb_addr_wb <= slave_i.dat (wb_addr_wb'left downto 0);
end if;
elsif (slave_i.adr (4 downto 2) = "101") then
-- Start NVM write
slave_o.dat <= slave_i.dat;
if (slave_i.we = '1') then
wb_data_reg <= slave_i.dat;
......@@ -280,13 +289,6 @@ if rising_edge (clk_i) then
end if;
end if;
end if;
end if;
end process;
end if;
end process;
end architecture;
hdl/xwb_ram_adapter.vhdl
View file @ f75d5e11
......@@ -122,14 +122,10 @@ architecture rtl of xwb_ram_adapter is
read_fault_p_o : out std_logic;
write_fault_p_o : out std_logic
);
end component;
signal addr_scrubber : unsigned (15 downto 0);
signal timeout_wb : unsigned (3 downto 0);
signal pwr, wr : std_logic;
type fsm_states is (idle, process_wb, scrubber_read);
signal fsm : fsm_states := idle;
......@@ -137,7 +133,7 @@ architecture rtl of xwb_ram_adapter is
signal we, re : std_logic;
signal addr : std_logic_vector (g_addr_width-1 downto 0);
signal data_in, data_out : std_logic_vector (31 downto 0);
signal bwe : std_logic_vector (3 downto 0);
signal bwe : std_logic_vector (3 downto 0);
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of rtl : architecture is "tmr";
......@@ -145,23 +141,17 @@ signal bwe : std_logic_vector (3 downto 0);
signal ack, done_r, done_w : std_logic;
signal data_read : std_logic_vector (31 downto 0);
attribute syn_encoding : string;
attribute syn_encoding of fsm : signal is "safe,onehot";
attribute syn_encoding : string;
attribute syn_encoding of fsm : signal is "safe,onehot";
begin
slave_o.ack <= ack;
slave_o.stall <= (not ack) and slave_i.cyc and slave_i.stb;
slave_o.err <= '0';
slave_o.int <= '0';
slave_o.rty <= '0';
process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
fsm <= idle;
......@@ -189,9 +179,9 @@ begin
if boot_done_i = '0' then
we <= slave_i.we;
elsif (g_is_iram and slave_i.we = '1') then
report "Attempt to write iram in runtime" severity error;
we <= '0';
fsm <= idle;
report "Attempt to write iram in runtime" severity error;
elsif (g_is_dram and slave_i.we = '1') then
if (g_addr_width = 15 and slave_i.adr (g_addr_width-1 downto g_addr_width-3) /= "111") then
we <= '0';
......@@ -214,10 +204,9 @@ begin
re <= '1';
addr <= std_logic_vector(addr_scrubber(g_addr_width-1 downto 0));
end if;
when process_wb =>
when process_wb =>
slave_o.dat <= data_out;
if ((re = '1' and done_r = '1') or (we = '1' and done_w = '1')) then
re <= '0';
we <= '0';
......@@ -226,9 +215,7 @@ begin
timeout_wb <= (others => '0');
end if;
when scrubber_read =>
if (done_r = '1') then
re <= '0';
fsm <= idle;
......@@ -238,10 +225,10 @@ begin
fsm <= idle;
end case;
end if;
end if;
end if;
end process;
ecc_simple : if g_data_width = 39 generate
ecc_simple : if g_data_width = 39 generate
ecc_circuitry : secded_ecc
generic map (
g_addr_width => g_addr_width
......@@ -277,9 +264,9 @@ ecc_simple : if g_data_width = 39 generate
read_fault_p_o => open,
write_fault_p_o => open
);
end generate ecc_simple;
end generate ecc_simple;
ecc_daec : if g_data_width = 42 generate
ecc_daec : if g_data_width = 42 generate
ecc_circuitry : secded_ecc_daec
generic map (
g_addr_width => g_addr_width
......@@ -288,7 +275,6 @@ ecc_daec : if g_data_width = 42 generate
clk_i => clk_i,
rst_i => rst_i,
d_i => data_in,
a_i => addr,
we_i => we and not done_w,
......@@ -315,8 +301,5 @@ ecc_daec : if g_data_width = 42 generate
read_fault_p_o => open,
write_fault_p_o => open
);
end generate ecc_daec;
end generate ecc_daec;
end architecture;
\ No newline at end of file
hdl/xwb_seu_reg.vhd
View file @ f75d5e11
......@@ -83,7 +83,6 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <='0';
desc_o <= (others => '0');
......
hdl/xwb_uart.vhd
View file @ f75d5e11
......@@ -78,7 +78,6 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <='0';
desc_o <= (others => '0');
......
hdl/xwb_wd_reg.vhd
View file @ f75d5e11
......@@ -70,7 +70,6 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <='0';
desc_o <= (others => '0');
......
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