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These are the [currently supported toolchains](https://ohwr.org/project/hdl-make/wikis/home#supported-tools). Note that Intel/Altera Quartus, Xilinx ISE and Xilinx Vivado are the best supported and tested ones, but Lattice and Microsemi ones should be working OK too.
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Missing tools that had been requested:
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- **Synopsys' Synplify**: the support for this tool was requested by users from NASA's Jet Propulsion Lab and reported in #30. |
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- **Synopsys' Synplify**: the support for this tool was requested by users from NASA's Jet Propulsion Lab and reported in #30.
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## Enforced compilation
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Feature suggested by @adrianf0 at feature request #43.
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Possibility to enforce compilation of certain additional files at the
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end, respecting order.
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Case: A single netlist file generated by Cadence contains some empty
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modules. Their functional description is in separate, RTL files.
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Because/thanks to solver, I don't see possibility to enforce compilation
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of those additional files at the end, so empty modules in a work
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library, a overwritten by the specific one. |
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