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aim is to solve typical problems connected with simulation and
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synthesis.
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# Simulation
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For the time being we are attached to Modelsim as the best tool for HDL simulation. All of the scripts are intended to use this tool.
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# Simulation
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For the time being we are attached to Modelsim as the best tool for HDL
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simulation. All of the scripts are intended to use this tool.
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When compiling VHDL files for simulation, one must ensure their correct
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order. In every project there is a dependency tree among files - one
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will be met.
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For Altera there is no tool for this purpose delivered by the vendor.
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The aim of the prepared scripts is to help the developer with this
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activity. They can automatically build dependency tree based on project
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file and source files and put them write them down in makefile-style.
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The complete instruction on using this is provided in [Document](/documents/47) .
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# Synthesis
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Synthesis of large projects is a time and resource-consuming process. It
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makes the edit-compile-test cycle unreasonably long and makes harder to
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introduce petty modifications to the hardware. Apart from that much of
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system resources like memory or CPU time are consumed and synthesis
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makes running other application harder. The solution for this problem is
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to set up a dedicated server for synthesis purpose only. This allows to
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delegate this demanding task to a fast machine, while the developer’s
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computer remains still useful.
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This work is done by the provided scripts. They support synthesis with
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xst, synplify and quartus\_sh (which is shell binding for Altera's
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Quartus IDE).
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The complete instruction on using this is provided in [Document](/documents/47) .
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