... | ... | @@ -8,8 +8,9 @@ Hdlmake generates multi-purpose makefiles for FPGA projects. It enables |
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local and remote synthesis, fetching modules' dependencies from
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repositories, creating Quartus/ISE project files. All of this can be
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done with a makefile command or with Hdlmake directly. It supports
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modularity, scalability, revision control systems. Hdlmake is free and
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distributed with GPL.
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modularity, scalability, revision control systems. Hdlmake is free, open
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and distributed with GPL. All you need to download is a single file
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(*hdlmake*).
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## Rationale
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... | ... | @@ -62,7 +63,6 @@ supports synthesis and simulation, they are used for both testbenches |
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and top modules. The major goal of the manifests is to describe the
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structure of the project:
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- what is the module's ancestor (if needed),
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- for parent modules; what modules it is made of? where to take them
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from? where to store them locally?
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- what are the local files, that should be used in synthesis or
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... | ... | @@ -115,7 +115,7 @@ is necessary to change the current directory to this one that contains a |
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manifest. From there \\verbhdlmake.py must be run with one or more
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arguments.
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## Makefile preparation (option -k)
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## Makefile preparation (no option)
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Makefile preparation is one of the most basic features that Hdlmake can
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be used for. It relieves a developer of creating makefiles by hand.
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... | ... | @@ -140,7 +140,7 @@ to figure out dependencies between them by analyzing each file's |
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content. They are next written down as a makefile in the testbench's
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directory.
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## Fetching submodules for a top module (option -f)
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## Fetching submodules for a top module (option -f or **make fetch**)
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Hdlmake offers a short way of describing project structures. It is
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assumed that a projects can consist of modules, that are stored in
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... | ... | @@ -152,7 +152,7 @@ For each module one can specify a target catalog with manifest variable |
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folder may be located anywhere in the filesystem. It must be though a
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relative path (Hdlmake supports only relative paths).
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## Synthesizing projects remotely (option -r)
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## Synthesizing projects remotely (option -r or **make remote**)
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Another valuable feature of Hdlmake is the ability to perform VHDL
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synthesis on a remote machine instead of running it on your desktop.
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... | ... | @@ -173,16 +173,11 @@ adventages: |
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collaborating developers share the same machine for synthesis they
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can always be sure that the synthesis will run correctly.
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In order to make command-line synthesis possible, for both Altera and
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Xilinx a project for the vendor's IDE must be created - this is Quartus
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and ISE respectively. For Xilinx a .tcl file must exist in addition.
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This file can be generated when selecting \`\`Project'' and then
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\`\`Generate .tcl script''.
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Synthesis server and username for logging in on the synthesis server can
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be specified with run the parameters:`--synth-server` and `--synth-user`
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accordingly.
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## Synthesizing projects locally (option -l)
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## Synthesizing projects locally (option -l or **make local**)
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It is also possible to perform synthesis on the local machine. For this
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purpose server and username are not necessary.
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