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Created with Raphaël 2.2.016Sep28Apr2610938Feb24Jan14Nov24Oct232221224Sep2327Aug1692131Jul201612115430Jun28272624232019181713121164224May21548Mar22Feb2123Jan31Oct30Jul274Jun26Apr1827Mar65329Feb23131024Jan23221825Oct626Aug239432126Jul151413121187429Jun2221201716151410976131May30272524201613111029Apr28272120181413121097628Mar2522171615119814Jan1312Upgrade to GPL v3 to match the source code licensing termsSimple 8-bit counter test for syn/sim, VHDL/VerilogInitial Altera Quartus tool moduleInitial Xilinx PlanAhead tool moduleInitial Mentor ModelSim tool moduleInitial Microsemi Libero tool moduleInitial Icarus Verilog tool moduleInitial Xilinx ISim tool moduleInitial Xilinx ISE tool moduleInitial ghdl tool moduleInitial Lattice Diamond tool moduleInitial Aldec Active-HDL tool moduleBase multi-tool support updateAdd a new test for Verilog remote synthesisAdd a new test for vhdl remote synthesisFix the include directive for vlogcomp [isim+verilog]Add some verilog tests to filterFix a problem in simulation isim testCreate a sim folder in filter testTests for simulation and synthesisCreate Binary Configuration File [issue 637]Hierachy Separator breaks ISE Synthesisfix argument parsingImplement --force switch handling__main__.py: better automatic flow dispatchingEncode correctly (BCD) project.vhd thingsMerge branch 'master' of ohwr.org:misc/hdl-makeminor fixesminor fixfix bug with missing generate_project_vhdAdd non-dependable files at the beg. of .xise listConvert project.vhd data according to t_sdb_synthesisaltera: support pre/post-flow scripts1.11.1fix issue: Wrong help messagefix annoying error msg when executing sim makefileadd --generate-project-vhd swtichenhance makefile writer (modelsim)makefile_writer.py:fix dependencies in vsim makefilecorrect 32/64 bit paths for xilinxsim.inimakefile_writer.py: Modelsim.ini path fix