Skip to content
Snippets Groups Projects
Select Git revision
  • 94-allow-absolute-paths-in-manifests
  • SKA-mods
  • add-post-include-mkfile-support-rebase
  • dag-solver protected
  • develop
  • develop-david
  • develop-david2
  • develop-extra_system_libs
  • develop-objdir
  • develop-objdir_via_options_to_write_makefile
  • dlamprid-arria5_fix
  • feat_1339
  • feat_svn_ise
  • fix-lattice-diamond-rebase
  • gsi
  • isyp
  • liberosoc-proasic3-support-rebase
  • liberosoc-proasic3-support-rebase2
  • master default
  • release-3.0
  • 3.3
  • 3.2
  • 3.1
  • 1.1
  • 1.0
  • 3.0
  • 2.1
  • 2.0
28 results
You can move around the graph by using the arrow keys.
Created with Raphaël 2.2.024Jul23222019161529Jun2897642131May302422201918171615530Apr2926191430Mar252423201713Oct24Jun25May27Apr2428Mar27169Feb872Jan3Dec18Nov1514137510Oct963216Sep28Apr2610938Feb24Jan14Nov24Oct232221224Sep2327Aug1692131Jul201612115430Jun28272624232019181713121164224May21548Mar22Feb2123Jan31Oct30Jul274Jun26Apr1827Mar65329Feb23131024Jan23221825Oct626Aug239432126Jul151413121187429Jun2221201716151410976131May30272524201613is_fetched_recursively is not used in the code: deleteGroup all the module plugins in a single classStart moving the module stuff to a dedicated foldermake_list_of_modules method is not used in the code: deleteA more ordered way to process the Manifest dict using superMove some core Module stuff to a new class and refactor Module constructorMove files and submodule contents to a new classMove incl_makefiles stuff from Module to ModuleSynthesis, as it's only used by the synthesis toolMove include_dir stuff at Module to ModuleSimulationFix VHDL test for Quartus, missing module pathMove the altera-related stuff at module.py to a new classClean the iverilog tool file: this need a revampBitfile_target is only used in the unused old iverilog recipeMove the simulation-related stuff at module.py to a new classMove the synthesis-related stuff at module.py to a new classA more structured Module classRefactor Manifest.py parse & processDisable the fetch --update optionThe flatten option for fetch action is not longer required: this is the default behavior nowAdd sim_top variable to complement syn_top: top_module is redundant nowTemporarly disable Git submodule recursive fetchingA little more of comments about Modules and PoolGet_dep_level detects potential loop issues in designs that are OK: demote the critical exception to a warning log message per offending fileChange the way the module_pool environment is set for a cleaner main processAction class uses redundant arguments: options and env are already embedded into modules_poolA little bit of refactoring for a better code understandingDependableFile class is not longer requiredFix wrong 'mkdir' command for Modelsim Linux makefilesMake the ISE tcl files a little more Windows friendly: delete quotes from 'echo'Change library slash separator for Modelsim makefiles accordingly with the O.S. in useImproved 'relpath' function for a better cross O.S. supportMove vlog included dirs at Modelsim-like makefiles to a new variableUse 'top_module.include_dirs' as the included directories for 'vlog' compilerModelsim-like Makefiles use some POSIX commands: replace with Windows equivalents if available or rely on GNU Win32 Coreutils otherwiseThe 'which' command is not available at Windows command lineFix fetch for Git submodules on Windows: Normalize the paths to use the O.S. specific path separatorTree function: Solving unused package dependencies and other improvementsThe flag close_fds=True does not work on Windows: check before spawning a subprocessUse a platform independent Python function to determine if a path is absolute or relativeAdapt Modelsim-like makefiles to the new DAG solverdag-solverdag-solver