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Add support to NVC simulator

Augusto Fraga Giachero requested to merge nvc-support into develop

NVC is an Open Source VHDL simulator that is in active development and making fast progress towards VHDL 2008 and 2019 support. It also seems to have a WIP implementation for compiling Verilog (not yet supported in this pull-request).

The command line interface is very similar to GHDL, requiring only some re-arrangement of the argument order.

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