VHDL parser does not correctly detect and remove character/string literals
The VHDL parser does not robustly detect and remove character/string literals. This affects both master, and 2014 far as I can see.
Currently, after removing comments, it searches for "
or '
characters, and removes everything that is between them.
This does not account for use of VHDL attributes, like
signalname'event, signalname'left, signalname'length
etc. A very
common occurrence of this is clock'event
.
The algorithm for detecting a string literal must be improved to not
remove attributes (and all content thereafter, up to the next "
or
'
).
Interestingly enough, this problem affects the test case (counter
),
but since there is not any "important" content after the 'event
in the
file, it does not show up as a problem.
architecture behv of counter is
signal Pre_Q: unsigned(7 downto 0);
begin
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= "00000000";
elsif (clock='1' and clock'event) then -- !! content parsing after this line will be incorrect !!
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
Q <= std_logic_vector(Pre_Q);
end behv;