instantiation without component declaration (VHDL)
In VHDL it is possible to instantiate a module directly from the work library:
DECODER : entity work.decode_8b10b_top
HDLmake doesn't handle such cases case.
In VHDL it is possible to instantiate a module directly from the work library:
DECODER : entity work.decode_8b10b_top
HDLmake doesn't handle such cases case.