If a module has "fetchto" variable defined, then all
it's modules are fetched to this destination. If the
variable is indefined, then it is taken the parent.

Now modules to be fetched are recognized properly

If one the connection data is not given when the program is run
(--synth-server, --synth-user), hdlmake checks if the missing
variable is set in env variables (HDLMAKE_SERVER and HDLMAKE_USER
respectively)

A manifest variable 'syn_name' has been introduced
instead of 'name'. This variables indicates the remote
directory to be used. If it is not set in the manifest, its value
is based on the syn_project variable.

An automatic flow has been added. This means that when there no
run arguments indicating what to do, hdlmake tries to guess
the action on its own basing on the manifest.

Manifest's target indicates what is the synthesis target
(xilinx/altera). This influences what kind of project for synthesis
is made (qpf, xise).

Manifest's action indicates, if the manifest is used for synthesis,
simulation or cannot be treated as a top manifest.

Add an option to the ModulePool for building list of all files
that are engaged in a project. This includes files that
are not listed in the manifests but are included in the
verilog sources